Teruhisa Shimizu

Instruction fetch and dispatch scheme with flag‐in‐cache/in‐IBR

Shigeya Tanaka, Takashi Hotta, Hideo Sawamoto, 1998 .

ISC Processor with Pseudo Vector Processing Feature

Kotaro Shimamura, Shigeya Tanaka, Takashi Hotta, 1995 .

WP 25.3 A 450MHz 64b RISC Processor using Multiple Threshold Voltage CMOS

Keiichi Higeta, Takashi Matsumoto, Nobuo Tamba, 2000 .

A superscalar RISC processor with pseudo vector processing feature

Kotaro Shimamura, Shigeya Tanaka, Hideo Sawamoto, 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

Instruction fetch and dispatch scheme with flag-in-cache/in-IBR

Shigeya Tanaka, Takashi Hotta, Hideo Sawamoto, 1998, Systems and Computers in Japan.

Random Modulation: Multi-Threshold-Voltage Design Methodology in Sub-2-V Power Supply CMOS

Kazuo Yano, Naoki Kato, Teruhisa Shimizu, 2000 .