Sheqin Dong

发表

Constraints generation for analog circuits layout

X. Hong, Qingsheng Hao, Song Chen, 2004, 2004 International Conference on Communications, Circuits and Systems (IEEE Cat. No.04EX914).

Buffer planning algorithm based on partial clustered floorplanning

Sheqin Dong, Xianlong Hong, Chung-Kuan Cheng, 2005, Sixth international symposium on quality electronic design (isqed'05).

VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation

Chung-Kuan Cheng, Sheqin Dong, Yici Cai, 2001 .

Ordered Escape routing for grid pin array based on Min-cost Multi-commodity Flow

Sheqin Dong, Fengxian Jiao, Sheqin Dong, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Novel and efficient min cut based voltage assignment in gate level

Tao Lin, Satoshi Goto, Sheqin Dong, 2011, 2011 12th International Symposium on Quality Electronic Design.

Fixed-outline floorplanning with constraints through instance augmentation

Yoji Kajitani, Sheqin Dong, Xianlong Hong, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Corner block list: an effective and efficient topological representation of non-slicing floorplan

Yici Cai, Jun Gu, Sheqin Dong, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

An accurate and efficient probabilistic congestion estimation model in x architecture

Sheqin Dong, Xianlong Hong, Yuchun Ma, 2007, SLIP '07.

VLSI floorplanning with boundary constraints based on corner block list

Yici Cai, Jun Gu, Sheqin Dong, 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

Fast evaluation of Bounded Slice-line Grid

Jun Gu, Sheqin Dong, Xianlong Hong, 2004, Journal of Computer Science and Technology.

Dynamic global buffer planning optimization based on detail block locating and congestion analysis

Yici Cai, Jun Gu, Sheqin Dong, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Evaluating a bounded slice-line grid assignment in O(nlogn) time

Yici Cai, Jun Gu, Sheqin Dong, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Buffer planning for 3D ICs

Satoshi Goto, Sheqin Dong, Xianlong Hong, 2009, 2009 IEEE International Symposium on Circuits and Systems.

A Fixed-outline Floorplanning Method Based on 2.5D

Qi Xie, Sheqin Dong, Sheqin Dong, 2008 .

A novel fixed-outline floorplanner with zero deadspace for hierarchical design

Satoshi Goto, Sheqin Dong, Chung-Kuan Cheng, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

An Analytical Approach to Incremental Floorplanning

Xin Li, Sheqin Dong, Xianlong Hong, 2007, 2007 International Conference on Communications, Circuits and Systems.

Floorplanning for 2.5-D system integration using multi-layer-BSG structure

Sheqin Dong, Xianlong Hong, Shuyi Zheng, 2006, 2006 IEEE International Symposium on Circuits and Systems.

An efficient algorithm to fixed-outline floorplanning based on instance augmentation

Sheqin Dong, Xianlong Hong, Rong Liu, 2005, Ninth International Conference on Computer Aided Design and Computer Graphics (CAD-CG'05).

A fast placement approach for large scale modules based on less flexibility first principles

Sheqin Dong, Xianlong Hong, Shaojun Wei, 2005, 2005 6th International Conference on ASIC.

Performance constrained floorplanning based on partial clustering [IC layout]

Sheqin Dong, Xianlong Hong, Chung-Kuan Cheng, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Fixed-outline floorplanning based on common subsequence

Sheqin Dong, Xianlong Hong, Rong Liu, 2005, ACM Great Lakes Symposium on VLSI.

LFF algorithm for heterogeneous FPGA floorplanning

Sheqin Dong, Xianlong Hong, Yuliang Wu, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

An improved P-admissible floorplan representation based on corner block list

Sheqin Dong, Xianlong Hong, Renshen Wang, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

VLSI module placement based on probability search space smoothing

Sheqin Dong, Xianlong Hong, Jun Gu, 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

FAST-CBL: a fast floorplanning algorithm based on corner block list representation

Sheqin Dong, Xianlong Hong, Yijie Zeng, 2004, 2004 International Conference on Communications, Circuits and Systems (IEEE Cat. No.04EX914).

Interconnection driven VLSI module placement based on quadratic programming and considering congestion using LFF principles

Sheqin Dong, Xianlong Hong, Zhong Yang, 2004, 2004 International Conference on Communications, Circuits and Systems (IEEE Cat. No.04EX914).

Module placement based on quadratic programming and rectangle packing using less flexibility first principle

Zhong Yang, Sheqin Dong, Xianlong Hong, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Corner block list representation and its application with boundary constraints

Yici Cai, Jun Gu, Sheqin Dong, 2004, Science in China Series F: Information Sciences.

Deterministic VLSI block placement algorithm using Less Flexibility First principle

Jun Gu, Sheqin Dong, Xianlong Hong, 2003, Journal of Computer Science and Technology.

Arbitrary convex and concave rectilinear block packing based on corner block list

Yici Cai, Jun Gu, Sheqin Dong, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

VLSI module placement with pre-placed modules and considering congestion using solution space smoothing

Jun Gu, Sheqin Dong, Xianlong Hong, 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

An optimum placement search algorithm based on extended Corner Block List

Yici Cai, Jun Gu, Shuo Zhou, 2002, Journal of Computer Science and Technology.

Module placement with boundary constraints using O-tree representation

Yici Cai, Jun Gu, Sheqin Dong, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Efficient VLSI module placement with solution space smoothing

Jun Gu, Sheqin Dong, Xianlong Hong, 2002, IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions.

Stairway compaction using corner block list and its applications with rectilinear blocks

Yici Cai, Jun Gu, Sheqin Dong, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Floorplanning with abutment constraints based on corner block list

Yici Cai, Jun Gu, Sheqin Dong, 2001, Integr..

VLSI/PCB placement with predefined coordinate alignment constraint based on sequence pair

Yici Cai, Jun Gu, Rui Liu, 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

A compact algorithm for placement design using corner block list representation

Jun Gu, Sheqin Dong, Xianlong Hong, 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

Floorplanning with abutment constraints and L-shpaed/T-shaped blocks baed on corner block list

Yici Cai, Jun Gu, Sheqin Dong, 2001, DAC '01.

ECBL: an extended corner block list with solution space including optimum placement

Jun Gu, Shuo Zhou, Sheqin Dong, 2001, ISPD '01.

VLSI block placement using less flexibility first principles

Jun Gu, Sheqin Dong, Xianlong Hong, 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

A non-slicing floorplanning algorithm using corner block list topological representation

Yici Cai, Jun Gu, Sheqin Dong, 2000, IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394).

A comparison of less flexibility first principles with simulated annealing

Sheqin Dong, Xianlong Hong, Shaojun Wei, 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

A FastPlacement Approach forLargeScale Modules Basedon LessFlexibility First Principles

Sheqin Dong, Xianlong Hong, Youliang Wu, 2005 .

Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree

Fan Guo, Sheqin Dong, Xianlong Hong, 2006, JCIS.

3D CBL: an efficient algorithm for general 3D packing problems

Sheqin Dong, Xianlong Hong, Yuchun Ma, 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

Wirelength-driven force-directed 3D FPGA placement

Sheqin Dong, Wentao Sui, Jinian Bian, 2010, GLSVLSI '10.

Physical Information Driven Packing Method in FPGA

Sheqin Dong, Wentao Sui, Jinian Bian, 2008 .