Y. Mizushima

发表

Investigation of stress-induced voiding inside and under VIAS in copper interconnects with “wing” pattern

H. Ehara, H. Matsuyama, T. Suzuki, 2008, 2008 IEEE International Reliability Physics Symposium.

Warpage-Free Ultra-Thinning Ranged from 2 to 5-um for DRAM Wafers and Evaluation of Devices Characteristics

T. Ohba, T. Nakamura, Y. Mizushima, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Ultra thinning 300-mm wafer down to 7-µm for 3D wafer Integration on 45-nm node CMOS using strained silicon and Cu/Low-k interconnects

H. Kitada, T. Ohba, K. Arai, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Development of sub 10-µm ultra-thinning technology using device wafers for 3D manufacturing of terabit memory

H. Kitada, T. Ohba, T. Eshita, 2010, 2010 Symposium on VLSI Technology.

Ultra thinning down to 4-µm using 300-mm wafer proven by 40-nm node 2Gb DRAM for 3D multi-stack WOW applications

H. Kitada, T. Ohba, K. Arai, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

A robust wafer thinning down to 2.6-μm for bumpless interconnects and DRAM WOW applications

T. Ohba, K. Arai, T. Nakamura, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Impact of Thermomechanical Stresses on Bumpless Chip in Stacked Wafer Structure

T. Ohba, Y. Mizushima, H. Kitada, 2013 .

Characterization of Warpages and Layout-Dependent Local-Deformations for Large Die 3D Stacking

Y. Mizushima, A. Doté, H. Kitada, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Observation of lattice spacing fluctuation and strain undulation around through-Si vias in wafer-on-wafer structures using X-ray microbeam diffraction

T. Ohba, N. Taoka, Y. Mizushima, 2014 .

Direct observation of vacancy defects in electroplated Cu films

A. Uedono, T. Suzuki, T. Nakamura, 2004, Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).

Stress migration phenomenon in narrow copper interconnects

H. Matsuyama, T. Kouno, S. Otsuka, 2007 .

Stress migration phenomena in narrow copper lines

H. Ehara, H. Matsuyama, T. Suzuki, 2006, 2006 IEEE International Integrated Reliability Workshop Final Report.

Influence of wafer thinning process on backside damage in 3D integration

Hiroshi Hashimoto, Tadao Nakamura, Takayuki Ohba, 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

Vacancy-type defects induced by grinding of Si wafers studied by monoenergetic positron beams

Takayuki Ohba, Nagayasu Oshima, Ryoichi Suzuki, 2014 .

Simple Modeling and Characterization of Stress Migration Phenomena in Cu Interconnects

Y. Mizushima, Tomoji Nakamura, Takashi Suzuki, 2006 .

Behavior of copper contamination on backside damage for ultra-thin silicon three dimensional stacking structure

Young Suk Kim, Takayuki Ohba, Akira Uedono, 2017 .

Impact of back-grinding-induced damage on Si wafer thinning for three-dimensional integration

Takayuki Ohba, Hideki Hashimoto, Akira Uedono, 2014 .

Review of wafer-level three-dimensional integration (3DI) using bumpless interconnects for tera-scale generation

Koji Fujimoto, Takayuki Ohba, Young-Suk Kim, 2015, IEICE Electron. Express.

45 nm-node BEOL integration featuring porous-ultra-low-k/Cu multilevel interconnects

S. Nakai, H. Kitada, T. Nakamura, 2005, Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..

Characterization of Local Strain around Through-Silicon Via Interconnects by Using X-ray Microdiffraction

Young Suk Kim, Takayuki Ohba, Shigeaki Zaima, 2011 .

Optimization of Via Bottom Cleaning for Bumpless Interconnects and Wafer-on-Wafer (WOW) Integration

T. Ohba, T. Ohba, Y. Mizushima, 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

Electrical characteristics of bumpless interconnects for through silicon via (TSV) and Wafer-On-Wafer (WOW) integration

P. Tzeng, T. Ohba, T. Ku, 2016, 2016 International Conference on Electronics Packaging (ICEP).

Thermal stress destruction analysis in low-k layer by via-last TSV structure

Y. Mizushima, H. Kitada, S. Sakuyama, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

Development of ultra-thinning technology for logic and memory heterogeneous stack applications

Tadao Nakamura, K. Suzuki, Takayuki Ohba, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.