Madhu K. Iyer

发表

RTL SAT simplification by Boolean and interval arithmetic reasoning

Kwang-Ting Cheng, Forrest Brewer, Ganapathy Parthasarathy, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Safety property verification using sequential SAT and bounded model checking

Kwang-Ting Cheng, Li-C. Wang, Ganapathy Parthasarathy, 2004, IEEE Design & Test of Computers.

A self-test methodology for IP cores in bus-based programmable SoCs

Kwang-Ting Cheng, Jing-Reng Huang, Madhu K. Iyer, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

SHIVA – A Fast Hybrid Constraint Solver for Circuits

Ganapathy Parthasarathy, Madhu K. Iyer, Tim Kwang-Ting Cheng, 2003 .

An efficient finite-domain constraint solver for circuits

Kwang-Ting Cheng, Li-C. Wang, Ganapathy Parthasarathy, 2004, Proceedings. 41st Design Automation Conference, 2004..

Software-based weighted random testing for IP cores in bus-based programmable SoCs

Kwang-Ting Cheng, Madhu K. Iyer, K. Cheng, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

Efficient conflict-based learning in an RTL circuit constraint solver

Kwang-Ting Cheng, Ganapathy Parthasarathy, Madhu K. Iyer, 2005, Design, Automation and Test in Europe.

Efficient reachability checking using sequential SAT

Kwang-Ting Cheng, Li-C. Wang, Ganapathy Parthasarathy, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

An efficient sequential SAT solver with improved search strategies

Kwang-Ting Cheng, Feng Lu, Li-C. Wang, 2005, Design, Automation and Test in Europe.

SATORI-a fast sequential SAT engine for circuits

Kwang-Ting Cheng, Ganapathy Parthasarathy, Madhu K. Iyer, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Effect of Noise on Analog Circuit Testing

Michael L. Bushnell, Madhu K. Iyer, 1999, J. Electron. Test..

Structural search for RTL with predicate learning

Kwang-Ting Cheng, Forrest Brewer, Ganapathy Parthasarathy, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Combining ATPG and symbolic simulation for efficient validation of embedded array systems

Kwang-Ting Cheng, Tao Feng, Magdy S. Abadir, 2002, Proceedings. International Test Conference.

A comparison of BDDs, BMC, and sequential SAT for model checking

Kwang-Ting Cheng, Li-C. Wang, Ganapathy Parthasarathy, 2003, Eighth IEEE International High-Level Design Validation and Test Workshop.

Efficient reachability checking using sequential SAT

Madhu K. Iyer, K. Cheng, G. Parthasarathy, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).