R. Vega

发表

Comparison study of tunneling models for Schottky field effect transistors and the effect of Schottky barrier lowering

R. Vega, 2006, IEEE Transactions on Electron Devices.

Three-Dimensional FinFET Source/Drain and Contact Design Optimization Study

T.-J.K. Liu, R. Vega, T.-J.K. Liu, 2009, IEEE Transactions on Electron Devices.

Reliability Modeling and Analysis of Hot-Carrier Degradation in Multiple-Fin SOI n-Channel FinFETs With Self-Heating

R. Vega, A. Dixit, C. Gupta, 2019, IEEE Transactions on Electron Devices.

Comparison of LER Induced Mismatch in NWFET and NSFET for 5-nm CMOS

R. Vega, C. Jha, A. Dixit, 2020, IEEE Journal of the Electron Devices Society.

Impact of Hot-Carrier Degradation on Drain-Induced Barrier Lowering in Multifin SOI n-Channel FinFETs With Self-Heating

T. Hook, R. Vega, A. Dixit, 2020, IEEE Transactions on Electron Devices.

Schottky Field Effect Transistors and Schottky CMOS circuitry

R. Vega, 2006 .

Metal Source/Drain Schottky Field Effect Transistors - a Proof of Concept

R. Vega, 2004 .

Advanced Source/Drain and Contact Design for Nanoscale CMOS

Reinaldo Vega, R. Vega, 2010 .

A Comparative Study of Dopant-Segregated Schottky and Raised Source/Drain Double-Gate MOSFETs

Tsu-Jae King Liu, R.A. Vega, T. Liu, 2008, IEEE Transactions on Electron Devices.

Benchmarking Power Delivery Network Designs at the 5-nm Technology Node

D. Dechene, R. Vega, N. Lanzillo, 2022, IEEE Transactions on Electron Devices.

Evaluation of 10-nm Bulk FinFET RF Performance—Conventional Versus NC-FinFET

Y. Chauhan, T. Hook, R. Vega, 2018, IEEE Electron Device Letters.

Dopant-Segregated Schottky Source/Drain Double-Gate MOSFET Design in the Direct Source-to-Drain Tunneling Regime

T. Liu, R. Vega, R.A. Vega, 2009, IEEE Transactions on Electron Devices.

Impact of Gamma-Ray Radiation on DC and RF Performance of 10-nm Bulk N-Channel FinFETs

R. Vega, A. Dixit, K. Aditya, 2020, IEEE Transactions on Device and Materials Reliability.

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

D. Liu, P. Oldiges, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

B. Lherron, D. Chanemougame, P. Oldiges, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Dopant-Segregated Schottky Junction Tuning With Fluorine Pre-Silicidation Ion Implant

T. Liu, R. Vega, 2010, IEEE Transactions on Electron Devices.

Study of Random Dopant Fluctuation Effects in Germanium-Source Tunnel FETs

Sung Hwan Kim, Changhwan Shin, T. Liu, 2011, IEEE Transactions on Electron Devices.

Effective Channel Mobility Extraction and Modeling of 10-nm Bulk CMOS FinFETs in Cryogenic Temperature Operation for Quantum Computing Applications

R. Vega, A. Dixit, Sumreti Gupta, 2023, IEEE Transactions on Electron Devices.

Accurate Modeling of Cryogenic Temperature Effects in 10-nm Bulk CMOS FinFETs Using the BSIM-CMG Model

R. Vega, A. Dixit, Sumreti Gupta, 2022, IEEE Electron Device Letters.

Understanding short channel mobility degradation by accurate external resistance decomposition and intrinsic mobility extraction

Emre Alptekin, Huiling Shang, Dechao Guo, 2015 .

Compact Model of a Bulk FinFET Quantum Dot Toward Single Chip Integration of Qubits and Control Electronics for Quantum Computing Applications

R. Vega, A. Dixit, D. Sharma, 2023, IEEE Transactions on Electron Devices.

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

G. Northrop, V. Sardesai, S. Narasimha, 2014, 2014 IEEE International Electron Devices Meeting.

Channel Geometry Impact and Narrow Sheet Effect of Stacked Nanosheet

Nicolas Loubet, Tenko Yamashita, Miaomiao Wang, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications

C. Park, N. Loubet, B. Haran, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications

M. Khare, B. Haran, N. Loubet, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

High-k metal gate fundamental learning and multi-Vt options for stacked nanosheet gate-all-around transistor

Nicolas Loubet, Tenko Yamashita, Sivananda Kanakasabapathy, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

The Effect of Random Dopant Fluctuation on Specific Contact Resistivity

T. Liu, R. Vega, V. Lee, 2010, IEEE Transactions on Electron Devices.

Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Jie Yang, Terence B. Hook, Andreas Knorr, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).