T. Oashi

A 1 V 46 ns 16 Mb SOI-DRAM with body control technique

K. Kyuma, T. Eimori, S. Maegawa, 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

Stress-induced voiding in nickel silicide

T. Oashi, H. Tanimoto, T. Futase, 2013 .

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

T. Eimori, Y. Inoue, T. Iwamatsu, 1994, IEEE International Solid-State Circuits Conference.

Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)

Hideto Hidaka, Katsuhiro Suma, Kazuyasu Fujishima, 1996 .

Stress-induced voids in Ni-Pt silicide: Disconnection of narrow (Ni-Pt)Si between gate canyons on wide active area

T. Oashi, H. Tanimoto, T. Futase, 2011, 2011 IEEE International Interconnect Technology Conference.

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues

M. Yabuuchi, T. Terano, H. Makino, 2008, IEEE Journal of Solid-State Circuits.

ULSI DRAM/SIMOX with stacked capacitor cells for low-voltage operation

Hideto Hidaka, T. Iwamatsu, Takahiro Tsuruda, 1993, Proceedings of IEEE International Electron Devices Meeting.

Approaches to extra low voltage DRAM operation by SOI-DRAM

T. Iwamatsu, Narumi Sakashita, Masahide Inuishi, 1998 .

Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM

T. Eimori, Y. Yamaguchi, M. Yamada, 1999 .