G. Lemieux

发表

Vector Processing as a Soft Processor Accelerator

Guy Lemieux, Christopher Han-Yu Chou, Jason Yu, 2009, TRETS.

Using sparse crossbars within LUT

Guy Lemieux, David M. Lewis, D. Lewis, 2001, FPGA '01.

Rapid synthesis and simulation of computational circuits in an MPPA

Guy Lemieux, David Grant, Graeme Smecher, 2009, FPT.

Cache Abstraction for Data Race Detection in Heterogeneous Systems with Non-coherent Accelerators

A. Hu, G. Lemieux, M. Young, 2022, ACM Transactions on Embedded Computing Systems.

Ramial Chipped Wood: the Clue to a Sustainable Fertile Soil

G. Lemieux, D. Germain, 2000 .

VEGAS: soft vector processor with scratchpad memory

Guy Lemieux, Christopher Han-Yu Chou, Aaron Severance, 2011, FPGA '11.

DropBack: Continuous Pruning During Training pdf

Guy Lemieux, Mieszko Lis, Maximilian Golub, 2018, ArXiv.

An improved "soft" eFPGA design and implementation strategy

Guy Lemieux, Resve A. Saleh, Victor Aken Ova, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays

Stephen D. Brown, M. Khellah, Guy G.F. Lemieux, 1996, VLSI Design.

Procrustes: a Dataflow and Accelerator for Sparse Deep Neural Network Training

Guy Lemieux, Amin Ghasemazar, Mieszko Lis, 2020, 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Hardware Performance Monitoring in Multiprocessors

Guy G.F. Lemieux, G. Lemieux, 1996 .

System-on-Chip: Reuse and Integration

Shahriar Mirabbasi, Guy Lemieux, Alan J. Hu, 2006, Proceedings of the IEEE.

System-on-Chip: Reuse and Integration Pre-designed and pre-verified hardware and software blocks can be combined on chips for many different applicationsVthey promise large productivity gains.

Shahriar Mirabbasi, Partha Pratim Pande, Mark R. Greenstreet, 2006 .

Mixing Low-Precision Formats in Multiply-Accumulate Units for DNN Training

O. Sentieys, G. Lemieux, Silviu-Ioan Filip, 2022, International Conference on Field-Programmable Technology.

Congestion-aware Global Routing using Deep Convolutional Generative Adversarial Networks

Tsung-Yi Ho, Jianli Chen, Andre Ivanov, 2019, 2019 ACM/IEEE 1st Workshop on Machine Learning for CAD (MLCAD).

A Survey and Taxonomy of GALS Design Styles

Guy Lemieux, Mark R. Greenstreet, Paul Teehan, 2007, IEEE Design & Test of Computers.

Full Deep Neural Network Training On A Pruned Weight Budget

Guy Lemieux, Mieszko Lis, Maximilian Golub, 2018, MLSys.

Automated Space/Time Scaling of Streaming Task Graph pdf

Guy Lemieux, Hossein Omidian, G. Lemieux, 2016, ArXiv.

Design of interconnection networks for programmable logic

Guy Lemieux, David A. Lewis, D. Lewis, 2003 .

Session details: Architecture

Guy Lemieux, G. Lemieux, 2008, Symposium on Field Programmable Gate Arrays.

FPGA defect tolerance: impact of granularity

Anthony J. Yu, Guy Lemieux, G. Lemieux, 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement

G. Lemieux, A. Yu, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Directional and single-driver wires in FPGA interconnect

Anthony J. Yu, Guy Lemieux, Marvin Tom, 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

Analytical Framework for Switch Block Design

Guy Lemieux, David M. Lewis, D. Lewis, 2002, FPL.

Circuit design of routing switches

Guy Lemieux, David M. Lewis, D. Lewis, 2002, FPGA '02.

Using Sparse Crossbars within LUT Clusters

David Lewis, Guy G.F. Lemieux, D. Lewis, 2001 .

Vector processing as a soft-core CPU accelerator

Guy Lemieux, Jason Yu, Christopher Eagleston, 2008, FPGA '08.

Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays

Shahriar Mirabbasi, Guy Lemieux, Edmund Lee, 2006, 2006 IEEE International Conference on Field Programmable Technology.

MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing

A. Ivanov, G. Lemieux, Zhonghua Zhou, 2023, ACM Trans. Design Autom. Electr. Syst..

Generating highly-routable sparse crossbars for PLDs

Guy Lemieux, David M. Lewis, Paul Leventis, 2000, FPGA '00.

Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew

Guy Lemieux, Aaron Severance, Ameer Abdelhadi, 2012, 2012 International Conference on Field-Programmable Technology.

Area, delay, power, and cost trends for metal-programmable structured ASICs (MPSAs)

Steven J.E. Wilton, Guy G.F. Lemieux, Usman Ahmed, 2009, 2009 International Conference on Field-Programmable Technology.

Boosting F MAX of Processor Pipelines using Intentional Memory Clock Skew

G. Lemieux, Ameer Abdelhadi, Aaron Severance, 2012 .

An efficient FPGA overlay for portable custom instruction set extensions

Guy Lemieux, Dirk Koch, Christian Beckhoff, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor

Guy Lemieux, Aaron Severance, G. Lemieux, 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

ZUMA: An Open FPGA Overlay Architecture

Guy Lemieux, Alexander Brant, G. Lemieux, 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.

VENICE: A Compact Vector Processor for FPGA Applications

G. Lemieux, Aaron Severance, 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.

The NUMAchine multiprocessor

Guy Lemieux, Tarek S. Abdelrahman, Zeljko Zilic, 2000, Proceedings 2000 International Conference on Parallel Processing.

Design and implementation of the NUMAchine multiprocessor

Guy Lemieux, Zeljko Zilic, Michael Stumm, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars

Guy Lemieux, Philip Brisk, Yehdhih Ould Mohammed Moctar, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition

Guy Lemieux, Steven J. E. Wilton, Jeffrey B. Goeders, 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

Scalable and deterministic timing-driven parallel placement for FPGAs

Guy Lemieux, Chris C. Wang, G. Lemieux, 2011, FPGA '11.

The impact of interconnect architecture on via-programmed structured ASICs (VPSAs)

Guy Lemieux, Steven J. E. Wilton, Usman Ahmed, 2010, FPGA '10.

PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess

Guy Lemieux, Xiao Dong, G. Lemieux, 2009, 2009 International Conference on Field-Programmable Technology.

Congestion-driven regional re-clustering for low-cost FPGAs

Darius Chiu, Guy G.F. Lemieux, Steve Wilton, 2009, 2009 International Conference on Field-Programmable Technology.

Replace: An incremental placement algorithm for field programmable gate arrays

Guy Lemieux, David Leong, G. Lemieux, 2009, 2009 International Conference on Field Programmable Logic and Applications.

GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering

Guy Lemieux, Steven J. E. Wilton, Julien Lamoureux, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing

Guy Lemieux, David Grant, G. Lemieux, 2008, TRETS.

GlitchLess: an active glitch minimization technique for FPGAs

Guy Lemieux, Steven J. E. Wilton, Julien Lamoureux, 2007, FPGA '07.

Un/DoPack: Re-Clustering of Large System-on-Chip Designs with Interconnect Variation for Low-Cost FPGAs

G. Lemieux, M. Tom, D. Leong, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

Logic block clustering of large designs for channel-width constrained FPGAs

Guy Lemieux, Marvin Tom, G. Lemieux, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Soft + + : An Improved Embedded FPGA Methodology for SoC Designs

R. Saleh, G. Lemieux, Victor O. Aken'Ova, 2007 .

Congestion Estimation and Localization in FPGAs : A Visual Tool for Interconnect Prediction

Guy Lemieux, Darius Chiu, David Yeager, 2007 .

On two-step routing for FPGAS

Guy Lemieux, Stephen Dean Brown, Daniel Vranesic, 1997, ISPD '97.

TinBiNN: Tiny Binarized Neural Network Overlay in about 5, 000 4-LUTs and 5mW pdf

Guy Lemieux, Aaron Severance, Satwant Singh, 2019, ArXiv.