S. Yamada

A new method for precise evaluation of dynamic recovery of negative bias temperature instability

T. Noguchi, E. Morifuji, S. Aota, 2005, Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005..

Fully Integrated Advanced Bulk FinFETs Architecture Featuring Partially-Insulating Technique for DRAM Cell Application of 40nm Generation and Beyond

Donggun Park, Byung-Il Ryu, Wouns Yang, 2006, 2006 International Electron Devices Meeting.

A new method for analyzing boron penetration and gate depletion using dual-gate PMOSFETs for high performance G-bit DRAM design

S. Yamada, R. Nagai, N. Takaura, 2001, ICMTS 2001. Proceedings of the 2001 International Conference on Microelectronic Test Structures (Cat. No.01CH37153).

Supply and threshold-Voltage trends for scaled logic and SRAM MOSFETs

E. Morifuji, F. Matsuoka, S. Matsuda, 2006, IEEE Transactions on Electron Devices.

A multi-gigabit DRAM technology with 6F/sup 2/ open-bit-line cell distributed over-driven sensing and stacked-flash fuse

H. Fujisawa, S. Narui, S. Miyatake, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

1.5 nm equivalent thickness Ta/sub 2/O/sub 5/ high-k dielectric with rugged Si suited for mass production of high density DRAMs

T. Sekiguchi, M. Nakamura, Y. Ohji, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

A Fully Integrated Low Voltage DRAM with Thermally Stable Gate-first High-k Metal Gate Process

Jong-Ho Lee, Junhee Lim, Juyeon Jang, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Ultra Low Voltage Operations in Bulk CMOS Logic Circuits with Dopant Segregated Schottky Source/Drain Transistors

J. Koga, Y. Toyoshima, F. Matsuoka, 2006, 2006 International Electron Devices Meeting.