Jong-Ho Lee

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

Hyoung-Joo Kim, Jong-Ho Lee, Jun-Young Park, 2015, IEEE Journal of Solid-State Circuits.

Emerging memory technologies for neuromorphic computing

Jong-Ho Lee, J. Bae, Suhwan Lim, 2018, Nanotechnology.

23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices

Hyun-Soo Park, Hyuk-Jun Kwon, Jong-Ho Lee, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

Yong Jae Lee, Hyun-Soo Park, Hyuk-Jun Kwon, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).