T. Hirayama

Quantum Cost Reduction of Reversible Circuits Using New Toffoli Decomposition Techniques

Katsuhisa Yamanaka, Md Belayet Ali, T. Hirayama, 2015, 2015 International Conference on Computational Science and Computational Intelligence (CSCI).

Exact Exponential Algorithm for Distance-3 Independent Set Problem

Takashi Hirayama, Katsuhisa Yamanaka, Shogo Kawaragi, 2019, IEICE Trans. Inf. Syst..

A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced Subgraphs

Takashi Hirayama, Katsuhisa Yamanaka, Yusuke Sano, 2022, FAW.

New Two-Qubit Gate Library with Entanglement

Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, 2016, 2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL).

A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits

Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani, 2014, IEICE Trans. Inf. Syst..

A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced Subgraphs

Katsuhisa Yamanaka, T. Hirayama, Yusuke Sano, 2022, IEICE Trans. Inf. Syst..