R. Gu

A 0.5-3.5 Gb/s low-power low-jitter serial data CMOS transceiver

R. Gu, J.M. Tran, Heng-Chih Lin, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

Fractional-N phase locked loop design and applications

R. Gu, S. Ramaswamy, 2007, 2007 7th International Conference on ASIC.

A 6.25Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications

Lin Wu, Wai Lee, V. Gupta, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

A 6.25GHz 1V LC-PLL in 0.13/spl mu/m CMOS

Wai Lee, R. Gu, Ah-Lyan Yee, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels

V. Gupta, R. Gu, B. Parthasarathy, 2005, IEEE Journal of Solid-State Circuits.

A transmit architecture with 4-tap feedforward equalization for 6.25/12.5Gb/s serial backplane communications

Lin Wu, Wai Lee, Song Wu, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

Programmable termination for CML I/O's in high speed CMOS transceivers

V. Gupta, R. Gu, B. Parthasarathy, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

An Improved Programmable Neural Network and VLSI Architecture Using BiCMOS Building Blocks

R. Gu, M. I. Elmasry, D. Zhang, 2021 .