A. Reznicek

发表

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

L. H. Vanamurth, D. Yang, T. Adam, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

T. Adam, T. Standaert, M. Khare, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

H. Sunamura, T. Yamamoto, B. Haran, 2010, 2010 Symposium on VLSI Technology.

Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain

T. Adam, J. Holt, B. Haran, 2006, 2009 Symposium on VLSI Technology.

Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)

C. Ouyang, D. Mocuta, P. O'Neil, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Temperature varying photoconductivity of GeSn alloys grown by chemical vapor deposition with Sn concentrations from 4% to 11%

A. Reznicek, Yi-Chiau Huang, T. Adam, 2016 .

Low-temperature growth of epitaxial (1 0 0) silicon based on silane and disilane in a 300 mm UHV/CVD cold-wall reactor

S. Shinde, A. Reznicek, D. Sadana, 2010 .

Optical properties of pseudomorphic Ge1−xSnx (x = 0 to 0.11) alloys on Ge(001)

M. Medikonda, A. Reznicek, Yi-Chiau Huang, 2014 .

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

T. Nagumo, N. Loubet, W. Schwarzenbach, 2012, 2012 Symposium on VLSI Technology (VLSIT).

High strain embedded-SiGe via low temperature reduced pressure chemical vapor deposition

A. Reznicek, D. Sadana, T. Adam, 2012 .

Effect of Germanium Concentration on the Dielectric Function of Strained Si1-xGex Films

M. Medikonda, V. Paruchuri, A. Reznicek, 2012, 2012 International Silicon-Germanium Technology and Device Meeting (ISTDM).

〈1 0 0〉 Dislocations in nickel-base superalloys: Formation and role in creep deformation

A. Reznicek, T. Link, A. Epishin, 2005 .

SIMS quantification of SiGe composition with low‐energy ion beams

J. Holt, A. Madan, A. Turansky, 2011 .

Effects of stress on the dielectric function of strained pseudomorphic Si1−xGex alloys from 0 to 75% Ge grown on Si (001)

Alain C. Diebold, Gangadhara Raja Muthinti, Thomas N. Adam, 2012 .

Low-Temperature Epitaxial Si, SiGe, and SiC in a 300mm UHV/CVD Reactor

S. Shinde, R. Murphy, A. Reznicek, 2010 .

Ultra-low resistivity in-situ phosphorus doped Si and SiC epitaxy for source/drain formation in advanced 20nm n-type field effect transistor devices

Nicolas Loubet, Bruce B. Doris, Walter Kleemeier, 2012 .

Strain and lattice engineering for Ge FET devices

Stephen W. Bedell, John A. Ott, Alexander Reznicek, 2006 .

First Experimental Demonstration of MRAM Data Scrubbing: 80 Mb MRAM with 40 nm junctions for Last Level Cache Applications

D. Edelstein, R. Johnson, J. Slaughter, 2021, International Electron Devices Meeting.

Inline monitoring of SiGe strain relaxed buffers (SRBs) using high-resolution X-ray diffraction: AM: Advanced metrology

N. Loubet, A. Reznicek, J. Gaudiello, 2016, 2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

M. Vinet, L. Grenouillet, T. Nagumo, 2012, 2012 International Electron Devices Meeting.

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

B. Jagannathan, N. Loubet, P. Kulkarni, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Amorphization/templated recrystallization method for changing the orientation of single-crystal silicon: An alternative approach to hybrid orientation substrates

Keith E. Fogel, Chun-Yung Sung, John A. Ott, 2005 .

Strain engineering for silicon CMOS technology

Keith E. Fogel, Stephen W. Bedell, Alexander Reznicek, 2005 .

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

K. Maitra, P. Kulkarni, T. Yamashita, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.