S. Fan

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

L. H. Vanamurth, D. Yang, T. Adam, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

D. Corliss, T. Standaert, R. Wong, 2017, 2017 Symposium on VLSI Technology.

Understanding and mitigating High-k induced device width and length dependencies for FinFET replacement metal gate technology

V. Narayanan, T. Ando, A. Madan, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices

A. Young, H. Jagannathan, J. Demarest, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Ti and NiPt/Ti liner silicide contacts for advanced technologies

F. Chafik, S. Jain, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

P. Oldiges, C. Park, N. Loubet, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Full metal gate with borderless contact for 14 nm and beyond

B. Haran, V. Narayanan, J. Bruley, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

B. Jagannathan, N. Loubet, P. Kulkarni, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology

H. Jagannathan, J. Demarest, M. Sankarapandian, 2022, International Electron Devices Meeting.

Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm

M. Belyansky, C. Prindle, A. Young, 2019, 2019 Symposium on VLSI Technology.