C. Wallace

A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell

P. Bai, C. Auth, V. Chikarmane, 2002, Digest. International Electron Devices Meeting,.

45nm High-k + metal gate strain-enhanced transistors

C. Auth, L. Shifren, K. Mistry, 2008, 2008 Symposium on VLSI Technology.

Reliability Modeling of Middle-Of-Line Interconnect Dielectrics in Advanced process nodes

C. Wallace, R. Kasim, J. Weber, 2023, IEEE International Reliability Physics Symposium.

Direct print EUV patterning of tight pitch metal layers for Intel 18A process technology node

K. Fischer, R. Bigwood, N. Moumen, 2022, Photomask Technology.

Advanced Node DTCO in the EUV Era

R. Brain, C. Wallace, A. Wei, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

From wafer-level gate-oxide reliability towards ESD failures in advanced CMOS technologies

M. Kerber, A. Kerber, A. Kerber, 2006, IEEE Transactions on Electron Devices.