K. Kellens

发表

Dual-channel technology with cap-free single metal gate for high performance CMOS in gate-first and gate-last integration

A. Hikavyy, G. Mannaert, T. Schram, 2011, 2011 International Electron Devices Meeting.

Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme

S. Chew, T. Schram, K. Devriendt, 2014 .

Dielectric reliability of 70nm pitch air-gap interconnect structures

G. Beyer, H. Bender, F. Sebaai, 2011 .

Integration and Dielectric Reliability of 30 nm Half Pitch Structures in Aurora® LK HM

G. Beyer, S. Demuynck, K. Croes, 2010 .

Air gap formation by UV-assisted decomposition of CVD material

G. Beyer, O. Richard, Y. Travaly, 2008 .

Use of MIR-FTIR and k-value Measurements to Assess Potential Solutions to Reduce Damage During Porous Low-k Integration

K. Kellens, N. Rochat, P. Verdonck, 2009 .

Investigation of Forming and Its Controllability in Novel HfO 2 -Based 1T1R 40nm-Crossbar RRAM Cells

K. Devriendt, O. Richard, H. Bender, 2011 .

Process control & integration options of RMG technology for aggressively scaled devices

S. Chew, T. Schram, K. Devriendt, 2012, Symposium on VLSI Technology.

Integration of Vertical Carbon Nanotube Bundles for Interconnects

M. Heyns, G. Groeseneken, K. Kellens, 2009, ECS Transactions.

Barrier and seed repair performance of thin RuTa films for Cu interconnects

Christopher J. Wilson, G. Beyer, E. Sleeckx, 2011 .

Integration and dielectric reliability of 30nm ½ pitch structures in Aurora ®LK HM

G. Beyer, S. Demuynck, K. Croes, 2009 .

Highly scalable effective work function engineering approach for multi-VT modulation of planar and FinFET-based RMG high-k last devices for (Sub-)22nm nodes

E. Simoen, E. Vecchio, H. Bender, 2013, 2013 Symposium on VLSI Technology.

Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOS

H. Bender, G. Eneman, N. Horiguchi, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

K. Ronse, S. Locorotondo, V. Truffert, 2010, 2010 Symposium on VLSI Technology.

Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

R. Rajagopalan, K. Ronse, S. Locorotondo, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).