J. Arnold

Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

M. Ieong, E. Cartier, V. Narayanan, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

D. Corliss, T. Standaert, R. Wong, 2017, 2017 Symposium on VLSI Technology.

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

G. Burbach, D. Greenlaw, S.F. Huang, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO/sub 2//metal stacks

K. Maitra, V. Narayanan, R. Carruthers, 2006, IEEE Electron Device Letters.