K. McStay

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

S. Narasimha, M. Hargrove, R. Pal, 2011, 2011 International Electron Devices Meeting.

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm2 SRAM and ultra low-k back end with eleven levels of copper

M. Belyansky, L. Black, J. Holt, 2006, 2009 Symposium on VLSI Technology.

Transistor Matching and Fin Angle Variation in FinFET Technology

T. Hook, K. McStay, Samarth Agarwal, 2015, IEEE Transactions on Electron Devices.

Optimizing History Effects in 65nm PD-SOI CMOS

E. Leobandung, G. Freeman, M.M. Pelella, 2006, 2006 IEEE international SOI Conferencee Proceedings.

45nm CMOS — Silicon Photonics Monolithic Technology (45CLO) for Next-Generation, Low Power and High Speed Optical Interconnects

Javier Ayala, Louis Medina, Kevin McStay, 2020, 2020 Optical Fiber Communications Conference and Exhibition (OFC).

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

G. Northrop, V. Sardesai, S. Narasimha, 2014, 2014 IEEE International Electron Devices Meeting.

Process technology for IBM 14-nm processor designs featuring silicon-on-insulator FinFETs

Paul C. Parries, Giuseppe La Rosa, Scott R. Stiffler, 2018, IBM J. Res. Dev..

Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond

Bernhard Wunder, Balaji Jayaraman, Subramanian S. Iyer, 2012, 2012 IEEE International Conference on IC Design & Technology.