S. Siddiqui

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

S. Narasimha, M. Hargrove, R. Pal, 2011, 2011 International Electron Devices Meeting.

A novel atomic layer oxidation technique for EOT scaling in gate-last high-к/metal gate CMOS technology

J. Shepard, J. Sudijono, S. Krishnan, 2011, 2011 International Electron Devices Meeting.

Impact of oxygen plasma on nitrided and annealed atomic layer deposited SiO2/high-k/metal gate for high-voltage input and output fin-shaped field effect transistor devices

H. G. Parks, E. Kaltalioglu, R. Pandey, 2017 .

Modification of porous silica particles with poly(acrylic acid)

S. Siddiqui, J. Siddiqui, R. Ottenbrite, 2000 .

Gate-Last I/O Transistors based on Stacked Gate-All-Around Nanosheet Architecture for Advanced Logic Technologies

A. Chou, B. Haran, N. Loubet, 2021, International Electron Devices Meeting.

Effect of plasma N2 and thermal NH3 nitridation in HfO2 for ultrathin equivalent oxide thickness

J. Shepard, V. Narayanan, S. Krishnan, 2013 .

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

G. Northrop, V. Sardesai, S. Narasimha, 2014, 2014 IEEE International Electron Devices Meeting.

Limits of Gate Dielectrics Scaling

D. Schepis, T. Ando, R. Pandey, 2018 .