A. Inada

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

T. Adam, T. Standaert, M. Khare, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

K. Maitra, P. Kulkarni, T. Yamashita, 2010, 2010 Symposium on VLSI Technology.

High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

M. Vinet, L. Grenouillet, T. Nagumo, 2012, 2012 International Electron Devices Meeting.

Full metal gate with borderless contact for 14 nm and beyond

B. Haran, V. Narayanan, J. Bruley, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

K. Maitra, P. Kulkarni, T. Yamashita, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.