Y. Tateshita

发表

Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process

Y. Tagawa, M. Saito, N. Nagashima, 2007, 2007 IEEE Symposium on VLSI Technology.

Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates

Y. Tagawa, M. Saito, N. Nagashima, 2007, 2007 IEEE International Electron Devices Meeting.

Three-dimensional structures for high saturation signals and crosstalk suppression in 1.20 μm pixel back-illuminated CMOS image sensor

Y. Tateshita, T. Hirayama, S. Arakawa, 2013, 2013 IEEE International Electron Devices Meeting.

Sub-pixel Architecture of CMOS Image Sensor Achieving over 120 dB Dynamic Range with less Motion Artifact Characteristics

K. Ohno, Y. Tateshita, H. Mizuno, 2019 .

High Performance and High Reliability Dual Metal CMOS Gate Stacks Using Novel High-k Bi-layer Control Technique

T. Ando, Y. Tagawa, M. Saito, 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Intercalation of lithium in r.f.-sputtered niobium oxide film as electrode material for lithium-ion batteries

Y. Tateshita, M. Baba, N. Kumagai, 1995 .

Novel Damascene Gate Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated by In situ Arsenic- and Boron-Doped Epitaxy

N. Nagashima, Y. Tateshita, Y. Kikuchi, 2010 .

Planar Metal–Oxide–Semiconductor Field-Effect Transistors with Raised Source and Drain Extensions Fabricated by In situ Boron-Doped Selective Silicon Epitaxy

N. Nagashima, Y. Tateshita, Y. Kikuchi, 2010 .

5.7 A 132dB Single-Exposure-Dynamic-Range CMOS Image Sensor with High Temperature Tolerance

Takahiro Iinuma, Tomohiko Asatsuma, Yorito Sakano, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

Channel-Stress Enhancement Characteristics for Scaled pMOSFETs by Using Damascene Gate With Top-Cut Compressive Stress Liner and eSiGe

N. Nagashima, Y. Tateshita, S. Yamakawa, 2009, IEEE Transactions on Electron Devices.

A $2.9\mu \mathrm{m}$ Pixel CMOS Image Sensor for Security Cameras with high FWC and 97 dB Single-Exposure Dynamic Range

Y. Tateshita, H. Ansai, A. Masagaki, 2021, International Electron Devices Meeting.

High Performance Dual Metal Gate CMOS with High Mobility and Low Threshold Voltage Applicable to Bulk CMOS Technology

T. Ando, Y. Tagawa, M. Saito, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

High-Performance Metal/High-$k$ n- and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on (100) Substrates

Y. Tateshita, N. Nagashima, H. Wakabayashi, 2009, IEEE Transactions on Electron Devices.

Tinv Scaling and Gate Leakage Reduction for n-Type Metal Oxide Semiconductor Field Effect Transistor with HfSix/HfO2 Gate Stack by Interfacial Layer Formation Using Ozone–Water-Last Treatment

T. Ando, M. Saito, N. Nagashima, 2008 .