M. Nakata

Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates

Y. Tagawa, M. Saito, N. Nagashima, 2007, 2007 IEEE International Electron Devices Meeting.

Indications for an ideal interface structure of oxynitride tunnel dielectrics

Y. Kamigaki, M. Nakata, Ziyuan Liu, 2009, 2009 IEEE International Reliability Physics Symposium.

Two-step annealing technique for leakage current reduction in chemical-vapor-deposited Ta/sub 2/O/sub 5/ film

M. Nakata, Y. Nishioka, H. Shinriki, 1989, IEEE Electron Device Letters.

High Performance and High Reliability Dual Metal CMOS Gate Stacks Using Novel High-k Bi-layer Control Technique

T. Ando, Y. Tagawa, M. Saito, 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

UV-O/sub 3/ and dry-O/sub 2/: Two-step-annealed chemical vapor-deposited Ta/sub 2/O/sub 5/ films for storage dielectrics of 64-Mb DRAMs

Hiroshi Shinriki, M. Nakata, M. Nakata, 1991 .

1.5 nm equivalent thickness Ta/sub 2/O/sub 5/ high-k dielectric with rugged Si suited for mass production of high density DRAMs

T. Sekiguchi, M. Nakamura, Y. Ohji, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

High-Performance Metal/High-$k$ n- and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on (100) Substrates

Y. Tateshita, N. Nagashima, H. Wakabayashi, 2009, IEEE Transactions on Electron Devices.

Ta/sub 2/O/sub 5/ capacitors' dielectric material for giga-bit DRAMs

Y. Kawamoto, H. Miki, K. Torii, 1995, Proceedings of International Electron Devices Meeting.