Y. Morand

发表

50 nm-Gate All Around (GAA)-Silicon On Nothing (SON)-devices: a simple way to co-integration of GAA transistors within bulk MOSFET process

T. Skotnicki, D. Dutartre, P. Ribot, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

A. Toffoli, J. Cluzel, O. Faynot, 2010, 2010 Symposium on VLSI Technology.

Electromigration failure modes in damascene copper interconnects

J. Torres, Y. Morand, Lucile Arnaud, 1998 .

High quality Germanium On Insulator wafers with excellent hole mobility

Yves Morand, Sorin Cristoloveanu, Laurent Clavelier, 2007 .

Fabrication of SiGe-On-Insulator by Improved Ge Condensation Technique

P. Rivallin, B. Vincent, Y. Morand, 2006, 2006 International SiGe Technology and Device Meeting.

Thermal stability enhancement of Ni-based silicides, germano-silicides and germanides using W and F implantation for 3D CMOS sequential integration

Yves Morand, Perrine Batude, Louis Hutin, 2014, 2014 International Workshop on Junction Technology (IWJT).

Metallic source and drain module for FDSOI MOSFETs applications

O. Faynot, M. Vinet, L. Hutin, 2010, 2010 International Workshop on Junction Technology Extended Abstracts.

Highly performant FDSOI pMOSFETs with metallic source/drain

O. Cueto, V. Balan, O. Faynot, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

New insights on strained-Si on insulator fabrication by top recrystallization of amorphized SiGe on SOI

M. Vinet, L. Grenouillet, Y. Morand, 2015, EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon.

Copper-SilK integration in a 0.18 /spl mu/m double level metal interconnect

Yves Morand, Christian Arvet, T. Mourier, 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

High hole mobility GeOI pMOSFETs with high-k / metal gate on Ge condensation wafers

S. Deleonibus, S. Cristoloveanu, Y. Morand, 2007, 2007 IEEE International SOI Conference.

Multilevel test structures for metal CMP integration application to Cu/SiO/sub 2/ damascene interconnect

Yves Morand, M. Fayolle, P. Gayet, 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).

Junction technology outlook for sub-28nm FDSOI CMOS

Laurent Grenouillet, Yves Morand, Maud Vinet, 2014, 2014 International Workshop on Junction Technology (IWJT).

Evaluation Of Ni(Si1-xGex) And Pt(Si1-xGex) Contact Resistance For FD-SOI PMOS Metallic Source And Drain

O. Cueto, F. Allain, M. Vinet, 2013 .

Characterization and simulation of signal propagation and crosstalk on advanced Cu-SiO/sub 2/ on-chip interconnects for high speed circuits

V. Arnal, Y. Morand, A. Farcy, 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

Performance Characterization of Advanced Interconnects on High Speed VLSI Circuits

C. Bermond, B. Fléchet, Y. Morand, 2000, 30th European Solid-State Device Research Conference.

In situ HCl etching of Si for the elaboration of locally misorientated surfaces

J. Hartmann, Y. Morand, D. Rouchon, 2007 .

Fabrication, structural and electrical properties of (1 1 0) localized silicon-on-insulator devices

P. Brianceau, T. Skotnicki, S. Monfray, 2010 .

In-situ Microwave Characterization of Medium-k HfO2 and High-k STO Dielectrics for MIM Capacitors Integrated in Back-End of Line of IC

A. Farcy, T. Lacrevaz, B. Fléchet, 2007, 2007 Asia-Pacific Microwave Conference.

Reliability Characterization of Moisture-Induced Degradation of Low-K Dielectric Behavior for Advanced Interconnects

G. Reimbold, A. Ionescu, Y. Morand, 1999 .

Electrical characterization of copper penetration effects in silicon dioxide

J. Cluzel, G. Reimbold, Y. Morand, 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

Electrical Characterization of Copper Penetration Effects in the Gate Oxide of MOS Devices

J. Cluzel, G. Reimbold, Y. Morand, 2001 .

Metal/Insulator/Semiconductor contacts for ultimately scaled CMOS nodes: Projected benefits and remaining challenges

H. Grampeix, E. Dubois, M. Vinet, 2016, 2016 16th International Workshop on Junction Technology (IWJT).

Ultra-thin dielectric insertions for contact resistivity lowering in advanced CMOS: Promises and challenges

E. Dubois, M. Vinet, L. Hutin, 2016 .

Copper-SiOC-AirGap integration in a double level metal interconnect

Y. Morand, M. Assous, L. Ulmer, 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).

Ge Enrichment Technique on SiGe/SOI Mesa Islands: a Localized GeOI Structures Fabrication Method

J. Damlencourt, Y. Morand, D. Rouchon, 2008, ECS Transactions.

Method of preparing a germanium layer from a substrate silicon-germanium-on-insulator

J. Damlencourt, B. Vincent, Y. Morand, 2007 .

METHOD FOR PRODUCING AREAS BASED Si1-y Ge y Ge DIFFERENT LEVELS ON THE SAME SUBSTRATE GERMANIUM CONDENSATION

J. Damlencourt, Y. Morand, L. Clavelier, 2006 .

Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

O. Rozeau, O. Faynot, M. Vinet, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Atomic Vapour Deposition (AVD™) Process for High Performance HfO 2 2 Dielectric Layers

X. Garros, M. Cassé, J. Mitard, 2004 .

Emerging silicon-on-nothing (SON) devices technology

Stephane Monfray, T. Skotnicki, D. Chanemougame, 2004 .

Optimized nickel silicide process formation for high performance sub-65nm CMOS nodes

F. Wacquant, A. Pouydebasque, V. Carron, 2004 .

Dopant Effect On NiGe Texture During Nickel Germanide Growth

O. Kermarrec, Y. Campidelli, F. Nemouchi, 2007 .

First 80 nm SON (Silicon-On-Nothing) MOSFETs with perfect morphology and high electrical performance

M. Haond, T. Skotnicki, S. Monfray, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Source and Drain Contact Module for FDSOI MOSFETs : Silicidation and Strain Engineering

David Cooper, Yves Morand, Jean-Michel Hartmann, 2013 .

Ultrathin (5 nm) SiGe-On-Insulator with high compressive strain (−2 GPa): From fabrication (Ge enrichment process) to in-depth characterizations

W. Schwarzenbach, O. Bonnin, J. Hartmann, 2014 .

Dual metallic source and drain integration on planar Single and Double Gate SOI CMOS down to 20nm: Performance and scalability assessment

O. Faynot, M. Vinet, D. Lafond, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A review of the mechanical stressors efficiency applied to the ultra-thin body & buried oxide fully depleted silicon on insulator technology

Pierre Morin, Sylvain Maitrejean, Frederic Allibert, 2016 .

Highly-performant 38 nm SON (silicon-on-nothing) P-MOSFETs with 9 nm-thick channels

M. Haond, T. Skotnicki, S. Monfray, 2002, 2002 IEEE International SOI Conference.

Stacking fault generation during relaxation of silicon germanium on insulator layers obtained by the Ge condensation technique

J. Damlencourt, B. Vincent, V. Delaye, 2007 .

The Ge condensation technique: A solution for planar SOI/GeOI co-integration for advanced CMOS technologies?

Yves Morand, Yves Campidelli, Sorin Cristoloveanu, 2008 .

Work function tuning through dopant scanning and related effects in Ni fully silicided gate for sub-45nm nodes CMOS

D. Delille, Y. Morand, S. Descombes, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Effect of sputter-etching conditions on the barrier characteristics and the process-induced defects in (Ti-W)/Si Schottky diodes

Y. Morand, D. Bauza, C. Mallardeau, 1989 .

Electrical Properties and Sputter-etched Induced Defects in Ti-W/Si Schottky Diodes

Y. Morand, D. Bauza, C. Mallardeau, 1989, ESSDERC '89: 19th European Solid State Device Research Conference.

A new FDSOI spin qubit platform with 40nm effective control pitch

M. Cassé, M. Vinet, N. Rambal, 2021, International Electron Devices Meeting.

TiN-CVD process optimization for integration with Cu-CVD

R. Pantel, Y. Morand, M. Proust, 1999 .

Bonded planar double-metal-gate NMOS transistors down to 10 nm

M. Vinet, D. Lafond, S. Deleonibus, 2005, IEEE Electron Device Letters.

Self-Aligned Planar Double-Gate MOSFETs by Bonding for 22-nm Node, With Metal Gates, High- $\kappa$ Dielectrics, and Metallic Source/Drain

M. Vinet, D. Lafond, S. Deleonibus, 2009, IEEE Electron Device Letters.

Optimizing RFSOI Performance through a T-shaped Gate and Nano-Second Laser Annealing Techniques

P. Chevalier, S. Kerdilès, S. Crémer, 2023, 2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

Copper metallization for advanced IC: requirements and technological solutions

Yves Morand, Y. Morand, 1999 .