S. Orain

发表

Ultra-Thin Fully Depleted SOI Devices with Thin BOX, Ground Plane and Strained Liner Booster

A. Toffoli, O. Faynot, T. Skotnicki, 2006, 2006 IEEE international SOI Conferencee Proceedings.

Stress Memorization Technique (SMT) Optimization for 45nm CMOS

P. Stolk, F. Leverd, F. Arnaud, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Method for Managing the Stress Due to the Strained Nitride Capping Layer in MOS Transistors

V. Fiori, S. Orain, C. Ortolland, 2007, IEEE Transactions on Electron Devices.

Gold Wire Bonding Induced Peeling in Cu/Low-k Interconnects: 3D Simulation and Correlations

V. Fiori, S. Orain, S. Gallois-Garreignot, 2007, 2007 International Conference on Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems. EuroSime 2007.

Numerical Analysis of the Reliability of Cu/low-k Bond Pad Interconnections Under Wire Pull Test: Application of a 3D Energy Based Failure Criterion

V. Fiori, S. Gallois-Garreignot, S. Orain, 2007, 2007 International Conference on Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems. EuroSime 2007.

Experimental investigation on the thermal contact resistance between gold coating and ceramic substrates

T. Nguyen, S. Orain, Y. Scudeller, 2001 .

Methodology to Determine the Toughness of a Brittle Thin Film by Nanoindentation

M. Verdier, S. Orain, M. Dupeux, 2006 .

Channel Cracking Technique For Toughness Measurement Of Sioch Low-K Films

S. Orain, M. Dupeux, M. Braccini, 2006 .

Mobility Enhancement by Strained Nitride Liners for 65nm CMOS Logic Design Features

Pierre Morin, S. Orain, C. Ortolland, 2006 .

Tensile Contact Etch Stop Nitride for nMOS Performance Enhancement: Influence of the Film Morphology

K. Barla, F. Arnaud, C. Ortolland, 2006 .

Reliability Issues in Cu/low-k Structures Regarding the Initiation of Stress-Voiding or Crack Failure

V. Fiori, X. Federspiel, S. Orain, 2006, EuroSime 2006 - 7th International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems.

90 nm node damascene copper stress voiding model and lifetime extrapolation methodology

X. Federspiel, S. Orain, 2004, IEEE International Integrated Reliability Workshop Final Report, 2004.

Multi-Level Cu Interconnects Integration and Characterization with Air Gap as Ultra-Low K Material Formed using a Hybrid Sacrificial Oxide / Polymer Stack

O. Cueto, J. de Pontcharra, S. Orain, 2007, 2007 IEEE International Interconnect Technology Conferencee.

Thermo‐Mechanical Modeling of Process Induced Stress: Layout Effect on Stress Voiding Phenomena

V. Fiori, S. Orain, S. Verrier, 2006 .

Use of genetic algorithms for the simultaneous estimation of thin films thermal conductivity and contact resistances

S. Orain, Y. Scudeller, Thierry Brousse, 2001 .

Thermal conductivity of ZrO2 thin films

Y. Scudeller, Thierry Brousse, S. Orain, 2000 .

A constitutive single crystal model for the silicon mechanical behavior: applications to the stress induced by silicided lines and STI in MOS technologies

S. Orain, Florian Cacho, G. Cailletaud, 2005, EuroSimE 2005. Proceedings of the 6th International Conference on Thermal, Mechanial and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2005..

Virtual Prototyping based Design Optimization of the Substrate, Leadframe, and Flip Chip Package Families with Low-k Technology

S. Orain, W.D. van Driel, T. Hauck, 2006, EuroSime 2006 - 7th International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems.

FEM-based method to determine mechanical stress evolution during process flow in microelectronics. Application to stress-voiding

S. Orain, X. Federspiel, J.-C. Barbé, 2004, 5th International Conference on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems, 2004. EuroSimE 2004. Proceedings of the.

Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress

G. Reimbold, G. Ghibaudo, S. Orain, 2004, IEEE Transactions on Electron Devices.