V. Sardesai

Assessment of fully-depleted planar CMOS for low power complex circuit operation

K. Tabakman, S. Wu, T. Kanarsky, 2011, 2011 International Electron Devices Meeting.

Ti and NiPt/Ti liner silicide contacts for advanced technologies

F. Chafik, S. Jain, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

High yielding self-aligned contact process for a 0.150-/spl mu/m DRAM technology

J. Gambino, J. Faltermeier, V. Sardesai, 2002 .

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

B. Lherron, D. Chanemougame, P. Oldiges, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

A 7nm CMOS technology platform for mobile and high performance compute application

J. Zeng, S. Samavedam, B. Senapati, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

G. Northrop, V. Sardesai, S. Narasimha, 2014, 2014 IEEE International Electron Devices Meeting.

Functional Testing of AI Cores through Thinned 3D I/O Buffer Dies in 3D Die-Stacked Modules

S. Skordas, D. Mcherron, K. Hosokawa, 2022, 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).