Q. Liang

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm2 SRAM and ultra low-k back end with eleven levels of copper

M. Belyansky, L. Black, J. Holt, 2006, 2009 Symposium on VLSI Technology.

Optimizing History Effects in 65nm PD-SOI CMOS

E. Leobandung, G. Freeman, M.M. Pelella, 2006, 2006 IEEE international SOI Conferencee Proceedings.