M. Zaleski

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm2 SRAM and ultra low-k back end with eleven levels of copper

M. Belyansky, L. Black, J. Holt, 2006, 2009 Symposium on VLSI Technology.

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

X. Chen, M. Khare, D. Tekleab, 2008, 2008 Symposium on VLSI Technology.

Microstructure of hardened and softened zirconia after xenon implantation

C. B. Carter, M. G. Norton, M. Zaleski, 1991 .

Full Copper Electrochemical Mechanical Planarization (Ecmp) as a Technology Enabler for the 45 and 32nm Nodes

M. C. Luche, M. Rivoire, M. Mellier, 2007, 2007 IEEE International Interconnect Technology Conferencee.