Tzu-Chiang Chen

A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology

Min Cao, Feng Yuan, Tsung-Lin Lee, 2010, 2010 International Electron Devices Meeting.

Design Space Analysis for Cross-Point 1S1MTJ MRAM: Selector–MTJ Cooptimization

Tahui Wang, W. Gallagher, J. Chiu, 2020, IEEE Transactions on Electron Devices.

Energy-Efficient Monolithic 3-D SRAM Cell With BEOL MoS2 FETs for SoC Scaling

V. Hu, Tzu-Chiang Chen, Chao-Ching Cheng, 2020, IEEE Transactions on Electron Devices.

Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiO $_{{x}}$ /Si Substrates Using Area-Selective CVD Technology

Kai-Shin Li, T. Lai, J. Shieh, 2019, IEEE Transactions on Electron Devices.

First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate

Kai-Shin Li, T. Lai, J. Shieh, 2019, 2019 Symposium on VLSI Technology.

Design Technology Co-Optimization for Cold CMOS Benefits in Advanced Technologies

Tzu-Chiang Chen, P. Liao, H. Chiang, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).