Luca Gaetano Amarù

发表

Robert K. Brayton, Giovanni De Micheli, Mathias Soeken, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Nanofabric power analysis: Biosequence alignment case study

Mariagrazia Graziano, Luca Gaetano Amarù, Maurizio Zamboni, 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET

Ogun Turkyilmaz, Fabien Clermidy, Giovanni De Micheli, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Digital, analog and RF design opportunities of three-independent-gate transistors

Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Mehdi Hasan, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains

Giovanni De Micheli, Mathias Soeken, Paolo Ienne, 2017, ACM Great Lakes Symposium on VLSI.

Optimizing Majority-Inverter Graphs with functional hashing

Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Vertically-stacked double-gate nanowire FETs with controllable polarity: From devices to regular ASICs

Yusuf Leblebici, Giovanni De Micheli, Luca Gaetano Amarù, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Towards structured ASICs using polarity-tunable Si nanowire transistors

Yusuf Leblebici, Giovanni De Micheli, Luca Gaetano Amarù, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Majority-Inverter Graph: A novel data-structure and algorithms for efficient logic optimization

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

New Logic Synthesis as Nanotechnology Enabler

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, 2015, Proceedings of the IEEE.

Data compression via logic synthesis

Giovanni De Micheli, Luca Gaetano Amarù, Andreas Peter Burg, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

BDS-MAJ: A BDD-based logic synthesis tool exploiting majority logic decomposition

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

A Sound and Complete Axiomatization of Majority-n Logic

Giovanni De Micheli, Luca Gaetano Amarù, Anupam Chattopadhyay, 2015, IEEE Trans. Computers.

A fast pruning technique for low-power inexact Circuit design

Giovanni De Micheli, Luca Gaetano Amarù, Krishna V. Palem, 2015, 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS).

High Speed Architectures for Finding the First two Maximum/Minimum Values

Luca Gaetano Amarù, Guido Masera, Maurizio Martina, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Reversible Logic Synthesis via Biconditional Binary Decision Diagrams

Giovanni De Micheli, Luca Gaetano Amarù, Anupam Chattopadhyay, 2015, 2015 IEEE International Symposium on Multiple-Valued Logic.

Integrated ESOP Refactoring for Industrial Designs

Giovanni De Micheli, Mathias Soeken, Patrick Vuillod, 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Enabling exact delay synthesis

Robert K. Brayton, Giovanni De Micheli, Mathias Soeken, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Inversion Minimization in Majority-Inverter Graphs

Giovanni De Micheli, Mathias Soeken, Eleonora Testa, 2016 .

Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

An MIG-based compiler for programmable logic-in-memory architectures

Rolf Drechsler, Giovanni De Micheli, Mathias Soeken, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Majority-based synthesis for nanotechnologies

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications

Luca Gaetano Amarù, Edith Beigné, Pierre-Emmanuel Gaillardon, 2016, 2016 17th Latin-American Test Symposium (LATS).

Logic optimization and synthesis: Trends and directions in industry

Patrick Vuillod, Luca Gaetano Amarù, Jiong Luo, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Multiple Independent Gate FETs: How many gates do we need?

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, 2015, The 20th Asia and South Pacific Design Automation Conference.

Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking

Robert Wille, Giovanni De Micheli, Luca Gaetano Amarù, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Wave pipelining for majority-based beyond-CMOS technologies

Rudy Lauwereins, Giovanni De Micheli, Mathias Soeken, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only)

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, 2015, FPGA.

Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, 2014, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

The Programmable Logic-in-Memory (PLiM) computer

Giovanni De Micheli, Luca Gaetano Amarù, Anupam Chattopadhyay, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Multi-level logic benchmarks: An exactness study

Giovanni De Micheli, Mathias Soeken, Patrick Vuillod, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Exact Synthesis of Majority-Inverter Graphs and Its Applications

Mathias Soeken, Luca Gaetano Amarù, Giovanni De Micheli, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization

Giovanni De Micheli, Enrico Macii, Massimo Poncino, 2015, ACM Great Lakes Symposium on VLSI.

Improvements to boolean resynthesis

Robert K. Brayton, Giovanni De Micheli, Mathias Soeken, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Advanced system on a chip design based on controllable-polarity FETs

Giovanni De Micheli, Jian Zhang, Luca Gaetano Amarù, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Notes on Majority Boolean Algebra

Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù, 2016, 2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL).

Majority Logic Synthesis for Spin Wave Technology

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, 2014, 2014 17th Euromicro Conference on Digital System Design.

LUT Mapping and Optimization for Majority-Inverter Graphs

Giovanni De Micheli, Mathias Soeken, Winston Haaswijk, 2016 .

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors

Giovanni De Micheli, Jian Zhang, Luca Gaetano Amarù, 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

Majority-Inverter Graph: A New Paradigm for Logic Optimization

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

System-level assessment and area evaluation of Spin Wave logic circuits

Rudy Lauwereins, Diederik Verkest, Luca Gaetano Amarù, 2014, 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

NEM relay design with biconditional binary decision diagrams

Giovanni De Micheli, Winston Haaswijk, Luca Gaetano Amarù, 2015, Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15).

A new basic logic structure for data-path computation (abstract only)

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, 2014, FPGA.

Exploiting Circuit Duality to Speed up SAT

Giovanni De Micheli, Alan Mishchenko, Luca Gaetano Amarù, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Biconditional BDD: A novel canonical BDD for logic synthesis targeting XOR-rich circuits

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A novel basis for logic rewriting

Giovanni De Micheli, Mathias Soeken, Winston Haaswijk, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

An efficient manipulation package for Biconditional Binary Decision Diagrams

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Inversion optimization in Majority-Inverter Graphs

Rudy Lauwereins, Giovanni De Micheli, Mathias Soeken, 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

Nanowire systems: technology and design

Luca Gaetano Amarù, Giovanni De Micheli, Pierre-Emmanuel Gaillardon, 2014, Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences.