A. Naeemi

发表

Compact Physics-Based Circuit Models for Graphene Nanoribbon Interconnects

J. Meindl, A. Naeemi, 2009, IEEE Transactions on Electron Devices.

Performance comparison between carbon nanotube and copper interconnects for GSI

J. Meindl, A. Naeemi, R. Sarvari, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Monolayer metallic nanotube interconnects: promising candidates for short local interconnects

J. Meindl, A. Naeemi, 2005, IEEE Electron Device Letters.

Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI)

J. Meindl, A. Naeemi, R. Sarvari, 2005, IEEE Electron Device Letters.

Conductance Modeling for Graphene Nanoribbon (GNR) Interconnects

J. Meindl, A. Naeemi, 2007, IEEE Electron Device Letters.

Electron Transport Modeling for Junctions of Zigzag and Armchair Graphene Nanoribbons (GNRs)

J. Meindl, A. Naeemi, 2008, IEEE Electron Device Letters.

Performance and Energy-per-Bit Modeling of Multilayer Graphene Nanoribbon Conductors

V. Kumar, A. Naeemi, S. Rakheja, 2012, IEEE Transactions on Electron Devices.

Design and Performance Modeling for Single-Walled Carbon Nanotubes as Local, Semiglobal, and Global Interconnects in Gigascale Integrated Systems

J. Meindl, A. Naeemi, 2007, IEEE Transactions on Electron Devices.

Performance Modeling for Single- and Multiwall Carbon Nanotubes as Signal and Power Interconnects in Gigascale Systems

J. Meindl, A. Naeemi, 2008, IEEE Transactions on Electron Devices.

Design and fabrication of low-loss horizontal and vertical interconnect links using air-clad transmission lines and through silicon vias

R. Bashirullah, P. Kohl, R. Saha, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Graphene Nanoribbon Spin Interconnects for Nonlocal Spin-Torque Circuits: Comparison of Performance and Energy Per Bit With CMOS Interconnects

A. Naeemi, S. Rakheja, 2012, IEEE Transactions on Electron Devices.

Compact physical models for multiwall carbon-nanotube interconnects

J. Meindl, A. Naeemi, 2006, IEEE Electron Device Letters.

Performance Modeling for Carbon Nanotube Interconnects in On-Chip Power Distribution

A. Naeemi, J. Meindl, Gang Huang, 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

System-level performance optimization and benchmarking for on-chip graphene interconnects

Chenyun Pan, A. Naeemi, Chenyun Pan, 2012, 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems.

Polylithic integration of electrical and optical interconnect technologies for gigascale fiber-to-the-chip communication

A. Naeemi, A.V. Mule', T. Gaylord, 2005, IEEE Transactions on Advanced Packaging.

Impact of Width Variation of Global Inductive VLSI Interconnect Line

Noha H. Mahmoud, R. Chandel, J. Meindl, 2020 .

Compact modeling of spin-transport parameters in semiconducting channels in non-local spin-torque devices

A. Naeemi, S. Rakheja, 2012, 2012 12th IEEE International Conference on Nanotechnology (IEEE-NANO).

Circuit-technology co-optimization of heterogeneous hierarchical network-on-chips

A. Naeemi, N. Kani, 2012, 2012 IEEE International Interconnect Technology Conference.

Compact physical models for multilevel interconnect crosstalk in gigascale integration (GSI)

J.A. Davis, J.D. Meindl, A. Naeemi, 2004, IEEE Transactions on Electron Devices.

Compact modeling and performance optimization of 3D chip-to-chip interconnects with transmission lines, vias and discontinuities

R. Bashirullah, P. Kohl, A. Naeemi, 2012, 2012 IEEE International Interconnect Technology Conference.

On-Chip Interconnect Networks at the End of the Roadmap: Limits and Nanotechnology Opportunities

A. Naeemi, A. Naeemi, A. barvan, 2006, 2006 International Interconnect Technology Conference.

Physical Modeling of Temperature Coefficient of Resistance for Single- and Multi-Wall Carbon Nanotube Interconnects

A. Naeemi, J. Meindl, A. Naeemi, 2007, IEEE Electron Device Letters.

Communicating Novel Computational State Variables: Post-CMOS Logic

A. Naeemi, S. Rakheja, A. Naeemi, 2013, IEEE Nanotechnology Magazine.

Modeling Interconnects for Post-CMOS Devices and Comparison With Copper Interconnects

S Rakheja, A Naeemi, A. Naeemi, 2011, IEEE Transactions on Electron Devices.

Spin-Orbit-Torque Material Exploration for Maximum Array-Level Read/Write Performance

Shan X. Wang, D. Ralph, Jianping Wang, 2020, International Electron Devices Meeting.

An upper limit for aggregate I/O interconnect bandwidth of GSI chips constrained by power dissipation

J. Meindl, A. Naeemi, J.D. Meindl, 2004, Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).

Interconnecting device opportunities for gigascale integration (GSI)

J.A. Davis, R. Venkatesan, J.D. Meindl, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Optical and electrical interconnect partition length based on chip-to-chip bandwidth maximization

J.D. Meindl, T.K. Gaylord, A. Naeemi, 2004, IEEE Photonics Technology Letters.

Interconnect Network Analysis of Many-Core Chips

A. Naeemi, A. Balakrishnan, A. Balakrishnan, 2011, IEEE Transactions on Electron Devices.

Compact Physical Models for Power Supply Noise and Chip/Package Co-Design of Gigascale Integration

Gang Huang, D.C. Sekar, J.D. Meindl, 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication

Gang Huang, J.D. Meindl, M. Bakir, 2007, 2007 IEEE Electrical Performance of Electronic Packaging.

Ultralow-Power Single-Wall Carbon Nanotube Interconnects for Subthreshold Circuits

A Naeemi, A. Naeemi, O Jamal, 2011, IEEE Transactions on Nanotechnology.

From Interconnect Materials and Processes to Chip Level Performance: Modeling and Design for Conventional and Exploratory Concepts

A. Naeemi, H. Simka, V. Huang, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).