Y. Kohama

A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking

Tadahiro Kuroda, Hiroki Ishikuro, Takayasu Sakurai, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Interference from power/signal lines and to SRAM circuits in 65nm CMOS inductive-coupling link

H. Ishikuro, N. Irie, K. Niitsu, 2007, 2007 IEEE Asian Solid-State Circuits Conference.

Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration

Tadahiro Kuroda, Hiroki Ishikuro, Kenichi Osada, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A High-Speed Inductive-Coupling Link With Burst Transmission

T. Sakurai, H. Ishikuro, T. Kuroda, 2009, IEEE Journal of Solid-State Circuits.

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking

Tadahiro Kuroda, Takayasu Sakurai, Noriyuki Miura, 2009, IEEE J. Solid State Circuits.

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM

Tadahiro Kuroda, Kenichi Osada, Kiichi Niitsu, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.