J. Park

A 22nm high performance embedded DRAM SoC technology featuring tri-gate transistors and MIMCAP COB

R. Brain, N. Lindert, J. Steigerwald, 2013, 2013 Symposium on VLSI Technology.

A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

P. Bai, N. Lindert, K. Mistry, 2008, 2008 IEEE International Electron Devices Meeting.

Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications

E. S. Jung, K. H. Hwang, J. S. Park, 2017, 2017 Symposium on VLSI Technology.

A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications

P. Bai, N. Lindert, I. Post, 2006, 2006 International Electron Devices Meeting.

Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application

A. Rahman, C. Tsai, P. Bai, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Non-Volatile RRAM Embedded into 22FFL FinFET Technology

P. Bai, C. English, A. Chen, 2019, 2019 Symposium on VLSI Technology.

Ovonic unified memory - a high-performance nonvolatile memory technology for stand-alone memory and embedded applications

T. Lowrey, M. Gill, J. Park, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

MRAM as Embedded Non-Volatile Memory Solution for 22FFL FinFET Technology

T. Ghani, C. Wiegand, O. Golonzka, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

J. Rizk, K. Soumyanath, P. VanDerVoorn, 2010, 2010 International Electron Devices Meeting.

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

G. Curello, W. Hafez, M. Kang, 2012, 2012 International Electron Devices Meeting.