T. Yamashita

发表

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

D. Corliss, T. Standaert, R. Wong, 2017, 2017 Symposium on VLSI Technology.

Process optimizations for NBTI/PBTI for future replacement metal gate technologies

Barry P. Linder, T. Ando, M. Wang, 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

K. Maitra, P. Kulkarni, T. Yamashita, 2010, 2010 Symposium on VLSI Technology.

Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs

T. B. Hook, T. Yamashita, T. E. Standaert, 2013, 2013 IEEE International Electron Devices Meeting.

Channel doping impact on FinFETs for 22nm and beyond

P. Oldiges, T. B. Hook, T. Yamashita, 2012, 2012 Symposium on VLSI Technology (VLSIT).

FinFET External Resistance Analysis by Extended Shift-and-Ratio Method

T. Yamashita, Zuoguang Liu, Xin He Miao, 2018, IEEE Transactions on Electron Devices.

Pinch Off Plasma CVD Deposition Process and Material Technology for Nano-Device Air Gap/Spacer Formation

D. Canaperi, Chanro Park, K. Cheng, 2018 .

Understanding and mitigating High-k induced device width and length dependencies for FinFET replacement metal gate technology

V. Narayanan, T. Ando, A. Madan, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices

A. Young, H. Jagannathan, J. Demarest, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Ti and NiPt/Ti liner silicide contacts for advanced technologies

F. Chafik, S. Jain, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

Strain, stress, and mechanical relaxation in fin-patterned Si/SiGe multilayers for sub-7 nm nanosheet gate-all-around device technology

O. Faynot, Nicolas Loubet, Shay Reboh, 2018 .

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

D. Liu, P. Oldiges, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

Sub- $10^{-9}~\Omega $ -cm2 n-Type Contact Resistivity for FinFET Technology

B. Haran, J. Demarest, O. Gluschenkov, 2016, IEEE Electron Device Letters.

Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability

H. Jagannathan, J. Demarest, O. Gluschenkov, 2017, 2017 Symposium on VLSI Technology.

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

O. Faynot, Y. Escarabajal, B. Lherron, 2014, 2014 IEEE International Electron Devices Meeting.

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

P. Oldiges, C. Park, N. Loubet, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond

Phil Oldiges, Wilfried Haensch, Andres Bryant, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Channel Geometry Impact and Narrow Sheet Effect of Stacked Nanosheet

Nicolas Loubet, Tenko Yamashita, Miaomiao Wang, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs

S. Narasimha, J. Johnson, M. Khare, 2015, Symposium on VLSI Technology.

Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications

C. Park, N. Loubet, B. Haran, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation

S. Ambrogio, A. Sebastian, T. Yamashita, 2021, 2021 IEEE International Reliability Physics Symposium (IRPS).

An analysis of stress evolution in stacked GAA transistors

Sylvain Maitrejean, Emmanuel Augendre, Nicolas Loubet, 2016, 2016 IEEE Silicon Nanoelectronics Workshop (SNW).

Imaging, Modeling and Engineering of Strain in Gate-All-Around Nanosheet Transitors

O. Faynot, N. Loubet, E. Augendre, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

High-k metal gate fundamental learning and multi-Vt options for stacked nanosheet gate-all-around transistor

Nicolas Loubet, Tenko Yamashita, Sivananda Kanakasabapathy, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Improved Air Spacer for Highly Scaled CMOS Technology

B. Haran, N. Loubet, Chanro Park, 2020, IEEE Transactions on Electron Devices.

Air spacer for 10nm FinFET CMOS and beyond

M. Wang, T. Yamashita, H. Bu, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Separation of interface states and electron trapping for hot carrier degradation in ultra-scaled replacement metal gate n-FinFET

Miaomiao Wang, James H. Stathis, Chia-Yu Chen, 2015, 2015 IEEE International Reliability Physics Symposium.

Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance

N. Loubet, T. Yamashita, J. A. Ott, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

K. Maitra, P. Kulkarni, T. Yamashita, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Tunneling currents and reliability of atomic-layer-deposited SiBCN for low-κ spacer dielectrics

R. G. Southwick, T. Yamashita, J. Stathis, 2014, 2014 IEEE International Reliability Physics Symposium.