D. Kong

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

D. Corliss, T. Standaert, R. Wong, 2017, 2017 Symposium on VLSI Technology.

Resistive Memory Process Optimization for High Resistance Switching Toward Scalable Analog Compute Technology for Deep Learning

M. Rasch, W. Haensch, V. Narayanan, 2021, IEEE Electron Device Letters.

Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications

C. Park, N. Loubet, B. Haran, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).