M. Tago

A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

T. Sakurai, N. Miura, T. Kuroda, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

Ultra-high-density 3D chip stacking technology

Kazumasa Tanida, Mitsuo Umemoto, Yoshihiro Tomita, 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..

Cu bump interconnections in 20 /spl mu/m pitch utilizing electroless tin-cap on 3D stacked LSI

K. Takahashi, Masamoto Tago, Y. Nemoto, 2001, Advances in Electronic Materials and Packaging 2001 (Cat. No.01EX506).

Advanced packaging technologies on 3D stacked LSI utilizing the micro interconnections and the layered microthin encapsulation

Yoshihiro Tomita, Yoshihiko Nemoto, Tadahiro Morifuji, 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

Au Bump Interconnection with Ultrasonic Flip-Chip Bonding in 20 µm Pitch

M. Tago, Y. Tomita, Y. Akiyama, 2003 .

An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing

Yasuhiro Morita, Tadahiro Kuroda, Koichi Nose, 2010, IEEE Journal of Solid-State Circuits.

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link

T. Sakurai, M. Inoue, N. Miura, 2007, IEEE Journal of Solid-State Circuits.

A novel "SMAFTI" package for inter-chip wide-band data transfer

M. Tago, K. Soejima, M. Kawano, 2006, 56th Electronic Components and Technology Conference 2006.