H. Noguchi

A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC Under DVS Environment

J. Miyakoshi, M. Yoshimoto, H. Kawaguchi, 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme

Shunsuke Okumura, Shusuke Yoshimoto, Masahiko Yoshimoto, 2009, 2009 10th International Symposium on Quality Electronic Design.

A 75-variable MIQP solver processor for real-time autonomous robot control

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2011, 2011 IEEE/SICE International Symposium on System Integration (SII).

Which is the best dual-port SRAM in 45-nm process technology? — 8T, 10T single end, and 10T differential —

H. Fujiwara, M. Yoshimoto, H. Kawaguchi, 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment

H. Fujiwara, M. Yoshimoto, H. Kawaguchi, 2007, 2007 IEEE Symposium on VLSI Circuits.

Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering

Masahiko Yoshimoto, Hidehiro Fujiwara, Koji Nii, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Parallel-processing VLSI architecture for mixed integer linear programming

Masahiko Yoshimoto, Hiroshi Kawaguchi, Hiroki Noguchi, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.