M. Rivier

Yield optimization of CMOS logic circuit designs

M. Rivier, 1987, 1987 Symposium on VLSI Circuits.

Probabilistic bulk production cost model by a continuation Monte Carlo simulation method

M. Rivier, I. J. Perez-Arriaga, 1991 .

Approximation of critical area of ICs with simple parameters extracted from the layout

M. Rivier, Frederic Duvivier, M. Rivier, 1995, Proceedings of International Workshop on Defect and Fault Tolerance in VLSI.

Use of a segmentation technique to analyze the variability of the yield of a mature CMOS SRAM

M. Rivier, Frederic Duvivier, B. Burtschy, 1993, Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.