N. Tamba

High-speed BiCMOS technology with a buried twin well structure

I. Masuda, A. Watanabe, T. Ikeda, 1987, IEEE Transactions on Electron Devices.

High speed BiCMOS VLSI technology with buried twin well structure

T. Ikeda, A. Watanabe, Y. Nishio, 1985, 1985 International Electron Devices Meeting.

A closed-form analysis of f/sub T/ for the bipolar transistor down to liquid nitrogen temperature

M. Weybright, J. Plummer, J. Shott, 1989, International Technical Digest on Electron Devices Meeting.

WP 25.3 A 450MHz 64b RISC Processor using Multiple Threshold Voltage CMOS

Keiichi Higeta, Takashi Matsumoto, Nobuo Tamba, 2000 .

A 450 MHz 64 b RISC processor using multiple threshold voltage CMOS

K. Mori, H. Takahashi, K. Higeta, 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

Hot-electron-induced minority-carrier generation in bipolar junction transistors

J. Shott, S.S. Wong, N. Tamba, 1990, IEEE Electron Device Letters.

A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM

Kunihiko Yamaguchi, Youji Idei, H. Nambu, 1992 .

A 1.5 ns 256 kb BiCMOS SRAM with 11 k 60 ps logic gates

Kunihiko Yamaguchi, H. Nambu, Nobuo Tamba, 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 27 GHz double polysilicon bipolar technology on bonded SOI with embedded 58 mu m/sup 2/ CMOS memory cells for ECL-CMOS SRAM applications

T. Hiramoto, T. Ikeda, M. Odaka, 1992, 1992 International Technical Digest on Electron Devices Meeting.

An 8ns 256k Bicmos Ram

N. Tamba, S. Miyaoka, M. Odaka, 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.