C. Raynaud

发表

Self-Heating effects on Static and Dynamic SOI Operation

D. Yachou, J. Gautier, C. Raynaud, 1993, ESSDERC '93: 23rd European solid State Device Research Conference.

Subthreshold Knks in Fully epleted SO1 MOSFET's

C. Raynaud, S. Krishnan, S. Cnstoloveanu, 1995 .

Fully-depleted 0.25 /spl mu/m SOI devices for low power RF mixed analog-digital circuits

O. Faynot, Simon Deleonibus, J. L. Pelloie, 1998, 1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199).

A 4H-SiC high power density VJFET as controlled current limiter

P. Godignon, C. Raynaud, D. Tournier, 2002, Conference Record of the 2002 IEEE Industry Applications Conference. 37th IAS Annual Meeting (Cat. No.02CH37344).

Technology pathfinders for low cost and highly integrated RF Front End modules

C. Raynaud, 2014, 2014 IEEE International Electron Devices Meeting.

State of the art 200 GHz passive components and circuits integrated in advanced thin SOI CMOS technology on High Resistivity substrate

Ph. Benech, F. Gianesello, D. Gloria, 2006, 2006 IEEE international SOI Conferencee Proceedings.

Design for millimeter-wave applications in silicon technologies

D. Belot, S.P. Voinigescu, F. Gianesello, 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

Two-dimensional simulations of the parasitic edge conduction in deep submicron fully depleted SOI NMOS devices

O. Faynot, C. Raynaud, P. Rivallin, 1997, 1997 IEEE International SOI Conference Proceedings.

Scalability of fully-depleted SOI technology into 0.13 /spl mu/m 1.2 V-1 V CMOS generation

O. Faynot, J. Cluzel, J. L. Pelloie, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

Impact of downscaling on high-frequency noise performance of bulk and SOI MOSFETs

J.-P. Raskin, F. Danneville, G. Dambrine, 2003, IEEE Transactions on Electron Devices.

High frequency characterization of SOI dynamic threshold voltage MOS (DTMOS) transistors

O. Faynot, C. Raynaud, A. Bracale, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

Impact of floating body and BS-tied architectures on SOI MOSFET's radio-frequency performances

C. Raynaud, F. Balestra, J. Boussey, 2000, 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).

Extraction of the main current components of floating-body partially-depleted SOI devices

O. Faynot, C. Tabone, C. Fenouillet-Beranger, 2000, 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).

SPICE modeling of 55 nm embedded SuperFlash® technology 2T memory cells

O. Rozeau, E. Nowak, C. Raynaud, 2015, Proceedings of the 2015 International Conference on Microelectronic Test Structures.

0.25 /spl mu/m SOI technologies performance for low-power radio-frequency applications

C. Raynaud, Francis Balestra, J. Boussey, 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

SOI CMOS technology for wireless applications: Current trends and perspectives

F. Gianesello, D. Gloria, C. Raynaud, 2010, 2010 IEEE International SOI Conference (SOI).

High frequency low noise potentialities of down to 65 nm technology nodes MOSFETs

D. Gloria, G. Dambrine, S. Lepilliet, 2005, European Gallium Arsenide and Other Semiconductor Application Symposium, GAAS 2005.

SOI technology performance and modelling

O. Faynot, C. Raynaud, J.L. Pelloie, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

High resistivity SOI CMOS technology for multi-standard RF frontends

F. Gianesello, D. Gloria, C. Raynaud, 2008, 2008 IEEE International SOI Conference.

Small-Size low losses WLAN and GSM/DCS diplexers integrated in a low cost 130 nm high resistivity SOI CMOS technology

A. Giry, F. Gianesello, D. Gloria, 2009, 2009 European Microwave Conference (EuMC).

Accurate determination of the main parameters from V/sub t/(V/sub b/) curves of fully-depleted SOI devices

O. Faynot, A. Toffoli, B. Giffard, 1995, Proceedings International Conference on Microelectronic Test Structures.

Thorough evaluation of Hot-Carrier Induced Degradation in Deep Submicron Thin-film UNIBOND and SIMOX N-MOSFETs

C. Raynaud, F. Balestra, J. Jomaah, 1998, 28th European Solid-State Device Research Conference.

Comparison between fully- and partially-depleted SOI MOSFET's for low-power radio-frequency applications

C. Raynaud, F. Balestra, Jalal Jomaah, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

State of the art integrated millimeter wave passive components and circuits in advanced thin SOI CMOS technology on high resistivity substrate

Ph. Benech, F. Gianesello, D. Gloria, 2005, 2005 IEEE International SOI Conference Proceedings.

A new parameter extraction method for ultra-thin oxide SOI MOSFET's

O. Faynot, Sorin Cristoloveanu, C. Raynaud, 1994, Proceedings. IEEE International SOI Conference.

Transient response after pulsed ionizing excitation of several buried oxides in fully-depleted SOI NMOS transistors

O. Gruber, C. Raynaud, J.L. Pelloie, 1997, 1997 IEEE International SOI Conference Proceedings.

A scalable SOI technology for three successive generations: 0.18, 0.13 and 0.1 /spl mu/m for low-voltage and low-power applications

O. Faynot, C. Raynaud, François Martin, 1996, 1996 IEEE International SOI Conference Proceedings.

A SOI CMOS reconfigurable output matching network for multimode multiband power amplifiers

A. Giry, C. Raynaud, G. Pares, 2015, 2015 IEEE MTT-S International Microwave Symposium.

1.8 dB insertion loss 200 GHz CPW band pass filter integrated in HR SOI CMOS Technology

F. Gianesello, D. Gloria, G. Dambrine, 2007, 2007 IEEE/MTT-S International Microwave Symposium.

Integration of multi-standard front end modules SOCs on high resistivity SOI RF CMOS technology

F. Gianesello, D. Gloria, C. Raynaud, 2010, 2010 IEEE Radio Frequency Integrated Circuits Symposium.

Small-size low losses GSM and DCS harmonic filters integrated in a low cost 130 nm high resistivity SOI CMOS technology

F. Gianesello, D. Gloria, C. Raynaud, 2010, 2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF).

Unified deep-submicron fully-depleted SOI MOSFET modeling for circuit simulation

Denis Flandre, Benjamin Iniguez, C. Raynaud, 1999 .

Sub-0.25 /spl mu/m ultra-thin SOI CMOS with a single N+ gate process for low-voltage and low-power applications

O. Faynot, Georges Guegan, C. Raynaud, 1996, 1996 IEEE International SOI Conference Proceedings.

Challenges of modeling the Split-Gate SuperFlash® Memory Cell with 1.1V Select Transistor

O. Rozeau, C. Raynaud, S. Martinie, 2016, 2016 International Conference on Microelectronic Test Structures (ICMTS).

High voltage devices integration into advanced CMOS technologies

C. Raynaud, F. Monsieur, O. Noblanc, 2008, 2008 IEEE International Electron Devices Meeting.

Self-heating effects on SOI devices and implication to parameter extraction

D. Yachou, C. Raynaud, J. Gautier, 1993, Proceedings of 1993 IEEE International SOI Conference.

(INVITED) Deep-submicron digital CMOS potentialities for millimeter-wave applications

D. Belot, F. Gianesello, C. Raynaud, 2008, 2008 IEEE Radio Frequency Integrated Circuits Symposium.

3D group-cross symmetrical inductor: A new inductor architecture with higher self-resonance frequency and Q factor dedicated to advanced HR SOI CMOS technology

F. Gianesello, D. Gloria, C. Raynaud, 2008, 2008 IEEE Radio Frequency Integrated Circuits Symposium.

5 GHz 1.4 dB NF CMOS LNA integrated in 130 nm High Resistivity SOI technology

F. Gianesello, D. Gloria, C. Raynaud, 2007, 2007 International Symposium on Integrated Circuits.

0.25 μm fully depleted SOI MOSFETs for RF mixed analog-digital circuits, including a comparison with partially depleted devices with relation to high frequency noise parameters

O. Faynot, Denis Flandre, L. Picheta, 2002 .

5GHz1.4dBNFCMOS LNAintegrated in130nmHighResistivity SOItechnology

Daniel Gloria, Frederic Gianesello, C. Raynaud, 2007 .

65 nm HR SOI CMOS Technology: emergence of Millimeter-Wave SoC

F. Gianesello, D. Gloria, G. Dambrine, 2007, 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.

Integration of cellular front end modules on advanced high resistivity SOI RF CMOS technology

D. Petit, F. Gianesello, D. Gloria, 2011, 2011 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications.

SOI-MOSFET parameters for variable channel lengths in the high temperature range (300-600 K)

Sorin Cristoloveanu, C. Raynaud, Francis Balestra, 1996, 1996 IEEE International SOI Conference Proceedings.

A comparison of 10 GHz frequency dividers in bulk and SOI 0.13 /spl mu/m CMOS technologies

V. Knopik, J.-M. Fournier, C. Raynaud, 2005, 2005 IEEE International SOI Conference Proceedings.

A GSM receiver base band in 0.25µ, 1.8V fully depleted SOI including a 4thorder serial ΣΔ A/D converter

C. Raynaud, J. Sevenhans, E. Compagne, 2001, Proceedings of the 27th European Solid-State Circuits Conference.

Integrated Inductors in HR SOI CMOS technologies: on the economic advantage of SOI technologies for the integration of RF applications

F. Gianesello, D. Gloria, C. Raynaud, 2007, 2007 IEEE International SOI Conference.

High performance submicron SOI devices with silicon film thickness below 50 nm

O. Faynot, B. Giffard, C. Raynaud, 1994, Proceedings. IEEE International SOI Conference.

Fully-depleted accumulation-mode PMOSFET for 0.2 /spl mu/m SOI technology

O. Faynot, C. Raynaud, J. L. Pelloie, 1995, 1995 IEEE International SOI Conference Proceedings.

Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture

Sorin Cristoloveanu, C. Raynaud, C. Tinella, 2002 .

High current 3D symmetrical inductor integrated in an advanced HR SOI CMOS technology targeting RF power applications

F. Gianesello, D. Gloria, C. Raynaud, 2009, 2009 IEEE Radio Frequency Integrated Circuits Symposium.

Comparison of hot-carrier degradation effects in inversion-mode and accumulation-mode fully depleted SOI MOSFETs

O. Faynot, S. Cristoloveanu, C. Raynaud, 1993, Proceedings of 1993 IEEE International SOI Conference.

A monolithic watt-level SOI LDMOS linear power amplifier with through silicon via for 4G cellular applications

S. Joblot, A. Giry, G. Bertrand, 2013, 2013 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications.

Integration of ultra wide band high pass filter using high performance inductors in advanced high resistivity SOI CMOS technology

Ph. Benech, P. Vincent, F. Gianesello, 2006, Digest of Papers. 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

Study of the deep-submicron SOI MOSFET leakage current behavior at high temperatures

Denis Flandre, Benjamin Iniguez, Joao Antonio Martino, 2000 .

A GSM receiver base band in 0.25µ, 1.8V fully depleted SOI including a 4 th order serial ΣΔ A/D converter

Jan Sevenhans, C. Raynaud, E. Compagne, 2001 .

Millimeter wave design with 65 nm LP SOI HR CMOS technology

D. Belot, F. Danneville, G. Dambrine, 2007, 2007 IEEE International SOI Conference.

Deep-submicron DC to RF SOI MOSFET characterization and modelling

Denis Flandre, Pascal Simon, C. Raynaud, 1999 .

High-frequency performance of submicrometer channel-length silicon MOSFETs

G. Guegan, G. Dambrine, J. Gautier, 1991, IEEE Electron Device Letters.

Floating body and hot carrier effects in ultra-thin film SOI MOSFETs

C. Raynaud, Francis Balestra, S. H. Renn, 1996 .

New floating-body effect in partially depleted SOI pMOSFET due to direct-tunneling current in the partial n+ poly gate

G. Guegan, S. Deleonibus, J. Pretet, 2008 .

Thorough Investigation of Kink-Related Excess Noise in Deep Submicron SOI N-MOSFETs on Unibond Substrate

Sebastien Haendler, J. L. Pelloie, C. Raynaud, 1999 .

Influence of device engineering on the analog and RF performances of SOI MOSFETs

Denis Flandre, Jean-Pierre Raskin, Stéphane Adriaensen, 2003 .

Impact of Latch Phenomenon on Low Frequency Noise in SOI MOSFETs

C. Raynaud, J. Jomaah, F. Balestra, 1996, ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference.

Reduced floating body effects in narrow channel SOI MOSFETs

S. Cristoloveanu, J. Pretet, C. Raynaud, 2002, IEEE Electron Device Letters.

Impact of downscaling on high-frequency noise performance of bulk and SOI MOSFETs

Jean-Pierre Raskin, Francois Danneville, C. Raynaud, 2004 .

Total dose behavior of partially depleted SOI dynamic threshold voltage MOS (DTMOS) for very low supply voltage applications (0.6-1 V)

O. Faynot, J. L. Pelloie, C. Raynaud, 1999 .

Total dose effects on a fully-depleted SOI NMOSFET and its lateral parasitic transistor

J. L. Pelloie, C. Raynaud, V. Ferlet-Cavrois, 1997 .

First-Si fully functional Bulk-PDSOI migration of low-power SRAM

Philippe Flatresse, C. Raynaud, R. Gwoziecki, 2005 .

High transmission performance integrated antennas on SOI substrate for VLSI wireless interconnects

J. Torres, F. Ndagijimana, P. Benech, 2005, Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..

RF Power NLDMOS Technology Transfer Strategy from the 130nm to the 65nm node on thin SOI

F. Morancho, S. Haendler, C. Raynaud, 2007, 2007 IEEE International SOI Conference.

Impact of front oxide quality on transient effects and low-frequency noise in partially and fully depleted SOI N-MOSFETs

S. Haendler, J. L. Pelloie, C. Raynaud, 2002 .

CMOS/SOI technologies for low-power and low-voltage circuits

O. Faynot, J. L. Pelloie, C. Raynaud, 1999 .

Total dose induced latch in short channel NMOS/SOI transistors

Olivier Faynot, J. L. Pelloie, C. Raynaud, 1998 .

Shrinking from 0.25 µm down to 0.12 µm SOI CMOS technology node: a contribution to 1/f noise in partially depleted n-MOSFETs

Christina De Meyer, C. Raynaud, Jalal Jomaah, 2002 .

A Novel Capacitor-less 1T-DRAM on Partially Depleted SOI pMOSFET based on Direct-tunneling Current in the Partial n+ Poly Gate

G. Molas, J. Pretet, Georges Guegan, 2009 .

First 15V complementary LDMOS transistors in thin SOI 65nm low power technology

F. Morancho, F. Gianesello, C. Raynaud, 2007, Proceedings of the 19th International Symposium on Power Semiconductor Devices and IC's.

70 GHz Fmax fully-depleted SOI MOSFET's for low power wireless applications

Denis Flandre, Jean-Pierre Raskin, C. Raynaud, 2000 .

Investigation of single and double gate SOI MOSFETs in Accumulation Mode for enhanced performances and reduced technological drawbacks

D. Flandre, C. Raynaud, B. Iniguez, 2000, 30th European Solid-State Device Research Conference.

65 nm RFCMOS technologies with bulk and HR SOI substrate for millimeter wave passives and circuits characterized up to 220 GHZ

F. Gianesello, D. Gloria, P. Benech, 2006, 2006 IEEE MTT-S International Microwave Symposium Digest.

Narrow-channel effects in LOCOS-isolated SOI MOSFETs with variable thickness

Sorin Cristoloveanu, T. Ernst, Dimitris E. Ioannou, 2000, 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).

Detailed Analysis of Short-Channel SOI DT-MOSFET

O. Faynot, T. Ernst, S. Cristoloveanu, 1999, 29th European Solid-State Device Research Conference.

Subthreshold kinks in fully depleted SOI MOSFET's

O. Faynot, S. Cristoloveanu, C. Raynaud, 1995, IEEE Electron Device Letters.

Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress

G. Reimbold, G. Ghibaudo, S. Orain, 2004, IEEE Transactions on Electron Devices.

Comparative Analysis of SOI Floating-Body and DTMOS with Bulk Devices for 1V Operation

O. Faynot, P. Flatresse, J. L. Pelloie, 1999 .

Charge collection in submicron CMOS/SOI technology

J. L. Pelloie, C. Raynaud, A. B. Campbell, 1997 .

Reliability of ultra-thin film deep submicron SIMOX nMOSFETs

S. Haendler, C. Raynaud, Jalal Jomaah, 2002 .

New floating-body effect in partially depleted SOI pMOSFET due to direct-tunneling current in the partial n+ poly gate

G. Guegan, S. Deleonibus, J. Pretet, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

Electrical analysis of mechanical stress induced by shallow trench isolation [MOSFETs]

G. Reimbold, G. Ghibaudo, C. Raynaud, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

Temperature dependence (300-600K) of parasitic bipolar effects in SOI-MOSFETs

O. Faynot, S. Cristoloveanu, C. Raynaud, 1997, 27th European Solid-State Device Research Conference.

Submicron SOI-MOSFETs for high temperature operation (300–600K)

Sorin Cristoloveanu, Olivier Faynot, C. Raynaud, 1997 .

What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?

F. Danneville, G. Dambrine, S. Lepilliet, 2003, IEEE Electron Device Letters.

Interface coupling and film thickness measurement on thin oxide thin film fully depleted SOI MOSFETs

G. Reimbold, O. Faynot, F. Allain, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

Investigation of the reliability of Unibond and SIMOX N-MOSFETs using charge pumping and noise techniques

C. Raynaud, Jalal Jomaah, F. Balestra, 1998 .

Insights on the transient response of fully and partially depleted SOI technologies under heavy-ion and dose-rate irradiations

O. Faynot, Claude Marcandella, C. Raynaud, 2002 .

On the subthreshold swing and short channel effects in single and double gate deep submicron SOI-MOSFETs

C. Raynaud, F. Balestra, F. Balestra, 1999 .

High voltage devices added to a 0.13/spl mu/m high resistivity thin SOI CMOS process for mixed analog-RF circuits

C. Raynaud, A. Perrotin, O. Bon, 2005, 2005 IEEE International SOI Conference Proceedings.

On the Design of High Performance RF Integrated Inductors on High Resistively Thin Film 65 nm SOI CMOS Technology

F. Gianesello, D. Gloria, C. Raynaud, 2008, 2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.