A. Cerdeira

发表

Modeling real junctions by a series combination of two ideal diodes with parallel resistance and its parameter extraction

A. Ortiz-Conde, F. Sánchez, M. Estrada, 2001 .

An efficient and accurate procedure to evaluate distortion in SOI FD MOSFET

D. Flandre, F.J. Garcia Sanchez, A. Cerdeira, 2001, 2001 International Semiconductor Device Research Symposium. Symposium Proceedings (Cat. No.01EX497).

Charge based compact model for bulk FinFETs

R. Ritzenthaler, M. Togo, C. Claeys, 2012, 2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS).

An advanced drain current model for DGMOSFETs including self-heating effects

A. Lázaro, B. Iñíguez, A. Cerdeira, 2012, 2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS).

Charge-based compact analytical model for triple-gate junctionless nanowire transistors

Bruna Cardoso Paz, Marcelo Antonio Pavanello, Antonio Cerdeira, 2016 .

Compact model for short-channel symmetric double-gate junctionless transistors

Bruna Cardoso Paz, Marcelo Antonio Pavanello, Antonio Cerdeira, 2015 .

Proposal of compact analytical modeling for trigate junctionless nanowire transistors

M. Estrada, A. Cerdeira, F. Avila-Herrera, 2015, 2015 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC).

A Compact Model for Organic Field-Effect Transistors With Improved Output Asymptotic Behaviors

B. Iñíguez, G. Horowitz, Y. Bonnassieux, 2013, IEEE Transactions on Electron Devices.

Compact model for short channel symmetric doped double-gate MOSFETs

B. Iñíguez, M. Estrada, A. Cerdeira, 2008 .

Temperature dependent compact modeling of gate tunneling leakage current in double gate MOSFETs

J. Sedlmeir, B. Iñíguez, A. Cerdeira, 2013 .

Analytical Compact Model for Transcapacitances of Junctionless Nanowire Transistors

A. Cerdeira, F. Avila-Herrera, M. Pavanello, 2021, 2021 IEEE Latin America Electron Devices Conference (LAEDC).

DC thermal numerical simulation of DG MOSFET

A. Lázaro, B. Iñíguez, A. Cerdeira, 2011, Proceedings of the 8th Spanish Conference on Electron Devices, CDE'2011.

Compact Capacitance Model for OTFTs at Low and Medium Frequencies

Antonio Cerdeira, Magali Estrada, Benjamin Iniguez, 2014, IEEE Transactions on Electron Devices.

Accurate modeling and parameter extraction method for organic TFTs

Antonio Cerdeira, Magali Estrada, Benjamin Iniguez, 2005 .

Modeling the behavior of charge carrier mobility with temperature in thin-film polymeric transistors

B. Iñíguez, M. Estrada, A. Cerdeira, 2010 .

Improved modeling of gate leakage currents for fin-shaped field-effect transistors

Denis Flandre, Antonio Cerdeira, Valeriya Kilchytska, 2013 .

Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications

Denis Flandre, Antonio Cerdeira, Jean-Pierre Raskin, 2007 .

ON DOUBLE-GATE MOSFETS AND FINFETS MODELING

D. Flandre, B. Iñíguez, M. Estrada, 2014 .

Compact model for long-channel cylindrical surrounding-gate MOSFETs valid from low to high doping concentrations

B. Iñíguez, A. Cerdeira, M. Cheralathan, 2011 .

Modeling of potentials and threshold voltage for symmetric doped double-gate MOSFETs

Antonio Cerdeira, Magali Estrada, Benjamin Iniguez, 2008 .

High-frequency compact analytical noise model for double-gate metal-oxide-semiconductor field-effect transistor

Antonio Cerdeira, Magali Estrada, Antonio Lazaro, 2009 .

Effect of active layer thickness on the electrical characteristics of polymer thin film transistors

B. Iñíguez, M. Deen, M. Estrada, 2010 .

Analysis of the Performance of an Inverter Circuit: Varying the Thickness of the Active Layer in Polymer Thin Film Transistors with Circuit Simulation

Antonio Cerdeira, Magali Estrada, Victor Cabrera, 2012 .

Application of the Symmetric Doped Double-Gate Model in Circuit Simulation Containing Double-Gate Graded-Channel Transistors

Marcelo Antonio Pavanello, Antonio Cerdeira, Joaquín Alvarado, 2009 .

Implementation of nanoscale double-gate CMOS circuits using compact advanced transport models

Giuseppe Iannaccone, Antonio Cerdeira, Enrico Sangiorgi, 2013, Microelectron. J..

Contribution of carrier tunneling and gate induced drain leakage effects to the gate and drain currents of fin–shaped field–effect transistors

S. I. Garduño, D. Flandre, M. Estrada, 2011 .

Analytic modeling of gate tunneling currents for nano-scale double-gate MOSFETs

D. Flandre, A. Cerdeira, M. Estrada, 2012, 2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS).

Analytical modeling of direct tunneling current through gate stacks for the determination of suitable high-k dielectrics for nanoscale double-gate MOSFETs

Antonio Cerdeira, Magali Estrada, Francois Lime, 2011 .

Analytical modeling of the gate tunneling leakage for the determination of adequate high-k dielectrics in double-gate SOI MOSFETs at the 22 nm node

R. Ritzenthaler, F. Lime, B. Iñíguez, 2010, DRC 2010.

Impact of Asymmetric Channel Configuration on the Linearity of Double-Gate SOI MOSFETs

D. Flandre, A. Cerdeira, D. Flandre, 2006, 2006 International Caribbean Conference on Devices, Circuits and Systems.

Modelling and extraction procedure for gate insulator and fringing gate capacitance components of an MIS structure

A. G. Martinez-Lopez, M. Estrada, A. Cerdeira, 2016 .

Crystalline-like temperature dependence of the electrical characteristics in amorphous Indium-Gallium-Zinc-Oxide thin film transistors

F. Lime, B. Iñíguez, M. Estrada, 2017 .

Analytical I–V and C–V models for symmetric double-gate AOSTFTs

M. Estrada, A. Cerdeira, Y. Hernández-Barrios, 2021 .

A Complete Charge-Based Capacitance Model for IGZO TFTs

F. Lime, B. Iñíguez, M. Estrada, 2019, IEEE Electron Device Letters.

A compact model and direct parameters extraction techniques For amorphous gallium-indium-zinc-oxide thin film transistors

E. Fortunato, P. Barquinha, B. Iñíguez, 2016 .

High Mobility Hf-In-ZnO TFTs, with HfO2 as Dielectric for Low Voltage Operation Range

S. I. Garduño, M. Estrada, A. Cerdeira, 2021, 2021 IEEE Latin America Electron Devices Conference (LAEDC).

EFFECT OF THE DISTRIBUTION OF STATES IN AMORPHOUS IN-GA-ZN-O LAYERS ON THE CONDUCTION MECHANISM OF THIN FILM TRANSISTORS ON ITS BASE

F. Lime, B. Iñíguez, M. Estrada, 2018 .

Characterization of HfO2 on Hafnium-Indium-Zinc Oxide HIZO layer metal-insulator-semiconductor structures deposited by RF sputtering

M. Estrada, A. Cerdeira, I. Garduño, 2015, 2015 30th Symposium on Microelectronics Technology and Devices (SBMicro).

Effect of the capture cross section of bulk traps in amorphous materials on the frequency dependence of the Capacitance-Voltage characteristic of MIS structures

B. Iñíguez, M. Estrada, A. Cerdeira, 2015, 2015 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC).

Bias stress study of Metal-Insulator-Semiconductor structures with pulsed laser deposited InGaZnO on atomic layer deposited HfO2

S. I. Garduño, M. Estrada, A. Cerdeira, 2015, 2015 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC).

Analysis of bulk and accumulation mobilities in n- and p-type triple gate junctionless nanowire transistors

A. Cerdeira, M. Pavanello, T. A. Ribeiro, 2017, 2017 32nd Symposium on Microelectronics Technology and Devices (SBMicro).

Double-gate junctionless transistor model including short-channel effects

Bruna Cardoso Paz, Marcelo Antonio Pavanello, Antonio Cerdeira, 2015 .

The Roles of the Gate Bias, Doping Concentration, Temperature and Geometry on the Harmonic Distortion of Junctionless Nanowire Transistors Operating in the Linear Regime

M. Estrada, A. Cerdeira, R. Trevisoli, 2014 .

Modelling of Thin Film Transistors for Circuit Simulation

A. Cerdeira, R. Picos, M. Estrada, 2007, 2007 14th International Conference on Mixed Design of Integrated Circuits and Systems.

Verilog-A implementation of a double-gate junctionless compact model for DC circuit simulations

A. Cerdeira, F. Avila-Herrera, J. Alvarado, 2016 .

Short channel continuous model for double-gate junctionless transistors

A. Cerdeira, M. Pavanello, B. Cardoso Paz, 2014, 2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS).

Non-linear behavior of Junctionless nanowire transistors operating in the linear regime

M. Estrada, A. Cerdeira, R. Trevisoli, 2013, 28th Symposium on Microelectronics Technology and Devices (SBMicro 2013).

Analysis of charges densities in multiple-gates SOI nMOS junctionless

M. Estrada, A. Cerdeira, R. Trevisoli, 2013, 28th Symposium on Microelectronics Technology and Devices (SBMicro 2013).

FD MOS SOI circuit to enhance the ratio of illuminated to dark current of a co-integrated a-Si: H photodiode

Denis Flandre, Antonio Cerdeira, Magali Estrada, 2003, Microelectron. Reliab..

Room temperature plasma oxidation: A new process for preparation of ultrathin layers of silicon oxide, and high dielectric constant materials

M. Estrada, A. Cerdeira, J. Tinoco, 2006 .

Unified extraction method for amorphous and polycrystalline TFT above threshold model parameters

A. Cerdeira, B. Iniguez, M. Estrada, 2002, Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611).

Adaption of triple gate junctionless MOSFETs analytical compact model for accurate circuit design in a wide temperature range

M. Estrada, A. Cerdeira, R. Doria, 2018, 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Features of the Nonlinear Harmonic Distortion in AOSTFTs

B. Iñíguez, A. Cerdeira, J. Tinoco, 2019, IEEE Transactions on Electron Devices.

A review of recent MOSFET threshold voltage extraction methods

Juin J. Liou, Antonio Cerdeira, Francisco J. García-Sánchez, 2002, Microelectron. Reliab..

Numerical dc self-heating in planar double-gate MOSFETs

A. Lázaro, B. Iñíguez, A. Cerdeira, 2011 .

An improved EKV model for partially depleted SOI devices

A. Cerdeira, J. Alvarado, 2005, 2005 2nd International Conference on Electrical and Electronics Engineering.

Gate leakage current partitioning in nanoscale double gate MOSFETs, using compact analytical model

S. I. Garduño, F. Lime, B. Iñíguez, 2012 .

Frequency and Voltage Dependence of the Capacitance of MIS Structures Fabricated With Polymeric Materials

B. Iñíguez, M. Estrada, A. Cerdeira, 2013, IEEE Transactions on Electron Devices.

Sensor readout circuit using AOSTFTs for IGZO (In-Ga-ZnO) sensors

B. Iñíguez, M. Estrada, A. Cerdeira, 2022, 2022 IEEE Latin American Electron Devices Conference (LAEDC).

Effect of variations in blend preparation on the properties of P3HT:PCBM blend solar cells

B. Iñíguez, M. Estrada, A. Cerdeira, 2010, 2010 27th International Conference on Microelectronics Proceedings.

An insight to mobility parameters for AOSTFTs, when the effect of both, localized and free carriers, must be considered to describe the device behavior

B. Iñíguez, M. Estrada, A. Cerdeira, 2018, Solid-State Electronics.

NEW METHOD FOR THE DETERMINATION OF CARRIER LIFETIME IN DIODES USING A SINUSOIDAL CURRENT PULSE

M. Estrada, A. Cerdeira, 1998 .

Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures

O. Faynot, M. Cassé, M. Vinet, 2022, 2022 IEEE Latin American Electron Devices Conference (LAEDC).

3D Simulation of Triple-Gate MOSFETs

D. Flandre, A. Cerdeira, V. Kilchytska, 2010, 2010 27th International Conference on Microelectronics Proceedings.

Characterization and design methodology for low-distortion MOSFET-C analog structures in multithreshold deep-submicrometer SOI CMOS technologies

D. Flandre, A. Cerdeira, V. Kilchytska, 2006, IEEE Transactions on Electron Devices.

A comparison of Spice-based and carrier transport based simulations of plasma spread in thyristors

A. Cerdeira, R. Quintero, 2002, Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611).

Quasi-three-dimensional spice-based simulation of the transient behavior, including plasma spread, of thyristors and over-voltage protectors

Antonio Cerdeira, Adelmo Ortiz-Conde, Rodolfo Quintero, 2002, Microelectron. Reliab..

Hafnium-Indium-Zinc oxide thin film transistors using HfO2 as gate dielectric, with both layers deposited by RF sputtering

M. Estrada, A. Cerdeira, R. Picos, 2016, 2016 31st Symposium on Microelectronics Technology and Devices (SBMicro).

On the series resistance in staggered amorphous thin film transistors

Antonio Cerdeira, Benjamín Iñíguez, Lluís F. Marsal, 2016, Microelectron. Reliab..

New procedure for the extraction of basic a-Si:H TFT model parameters in the linear and saturation regions

F. J. Garcia Sanchez, Antonio Cerdeira, Adelmo Ortiz-Conde, 2001 .

Internal Fields in Amorphous pin Diodes

A. Ortiz-Conde, M. Estrada, A. Cerdeira, 2001 .

A simple procedure to extract the threshold voltage of amorphous thin film MOSFETs in the saturation region

Adelmo Ortiz-Conde, Antonio Cerdeira, Magali Estrada, 2001 .

Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation

Denis Flandre, Marcelo Antonio Pavanello, Rodrigo Trevisoli Doria, 2008, Microelectron. J..

Optimization of the i-layer width of Cr-a-Si:H PIN X-ray detectors

M. Estrada, A. Cerdeira, I. Pereyra, 2001 .

High deposition rate a-Si:H layers from pure SiH4 and from a 10% dilution of SiH4 in H2

A. Cerdeira, M. Estrada, Inés Pereyra, 2000 .

Characteristics of High Deposition Rate Pin Diodes from Pure SiH and 10% Dilution of SiH in H

Antonio Cerdeira, Magali Estrada, Inés Pereyra, 2000 .

Modeling of reverse current behavior in amorphous thin and thick p-i-n diodes

A. Cerdeira, M. Estrada, M. Estrada, 2000 .

Effects of impurity concentration, hydrogen plasma process and crystallization temperature on poly-crystalline films obtained from PECVD a-Si: H layers

Antonio Cerdeira, Rodolfo Zolá García-Lozano, Magali Estrada, 2003, Microelectron. Reliab..

Gate leakage currents model for FinFETs implemented in Verilog‐A for electronic circuits design

Denis Flandre, Antonio Cerdeira, Valeriya Kilchytska, 2014 .

Extraction method for polycrystalline TFT above and below threshold model parameters

Adelmo Ortiz-Conde, F. J. Garcia Sanchez, Antonio Cerdeira, 2002 .

Organic thin-film transistor bias-dependent capacitance compact model in accumulation regime

Antonio Cerdeira, Benjamín Iñíguez, Lluís F. Marsal, 2012, IET Circuits Devices Syst..

Analytical Current–Voltage Model for Double-Gate a-IGZO TFTs With Symmetric Structure for Above Threshold

B. Iñíguez, M. Estrada, A. Cerdeira, 2020, IEEE Transactions on Electron Devices.

Influence of low-temperature annealing on the dielectric characteristics and final parameters of SiO2 MIS thin film transistors

M. Estrada, A. Cerdeira, Y. Matsumoto, 1997 .

Influence of P3HT: PCBM blend preparation on the active layer morphology and cell degradation

Antonio Cerdeira, Benjamín Iñíguez, Lluís F. Marsal, 2011, Microelectron. Reliab..

MIS polymeric structures and OTFTs using PMMA on P3HT layers

Antonio Cerdeira, Magali Estrada, Benjamin Iniguez, 2008 .

Full capacitance model, considering the specifics of amorphous oxide semiconductor thin film transistors structures

B. Iñíguez, M. Estrada, A. Cerdeira, 2019, Solid-State Electronics.

Drain current model for short-channel triple gate junctionless nanowire transistors

Bruna Cardoso Paz, Mikaël Casse, Sylvain Barraud, 2016, Microelectron. Reliab..

Effect of interface charge on the dc bias stress-induced deformation and shift of the transfer characteristic of amorphous oxide thin-film transistors

Antonio Cerdeira, Benjamín Iñíguez, Magali Estrada, 2012, Microelectron. Reliab..

Dynamic Validation of the Full Model for AOSTFTs using a Ring Oscillator based on a-IGZO TFTs

B. Iñíguez, M. Estrada, A. Cerdeira, 2020, 2020 IEEE Latin America Electron Devices Conference (LAEDC).

Dynamic Simulation of a-IGZO TFT Circuits Using the Analytical Full Capacitance Model (AFCM)

B. Iñíguez, M. Estrada, A. Cerdeira, 2021, IEEE Journal of the Electron Devices Society.

Temperature dependence of the electrical characteristics up to 370 K of amorphous In-Ga-ZnO thin film transistors

Antonio Cerdeira, Magali Estrada, Marcelo Antonio Pavanello, 2016, Microelectron. Reliab..

Compact DC and Quasi-Static Capacitances Modeling of a-Si:H TFTs, Including Parasitic Capacitances

F. Lime, B. Iñíguez, M. Estrada, 2021, IEEE Transactions on Electron Devices.

DC self-heating effects modelling in SOI and bulk FinFETs

Antonio Lázaro, Antonio Cerdeira, Juan Bautista Roldán, 2015, Microelectron. J..

New procedure for the extraction of a-Si:H TFTs model parameters in the subthreshold region

Antonio Cerdeira, Magali Estrada, M. Estrada, 2003 .

Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range

M. Estrada, A. Cerdeira, R. Doria, 2019, Solid-State Electronics.

RF modeling of 40‐nm SOI triple‐gate FinFET

Antonio Cerdeira, Jean-Pierre Raskin, A. G. Martinez-Lopez, 2015 .

Study of potential high-k dielectric for UTB SOI MOSFETs using analytical modeling of the gate tunneling leakage

Antonio Cerdeira, Magali Estrada, Francois Lime, 2011 .

From double to triple gate: Modeling junctionless nanowire transistors

Sylvain Barraud, Gilles Reimbold, Olivier Faynot, 2015, EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon.

RF compact small-signal model for SOI DG-MOSFETs

J.-P. Raskin, A. Cerdeira, M. Estrada, 2010, 2010 27th International Conference on Microelectronics Proceedings.

Automatic parameter extraction techniques in IC-CAP for a compact double gate MOSFET model

Antonio Cerdeira, Benjamin Iniguez, Ghader Darbandy, 2013 .

Amorphous silicon carbide TFTs

B. Iñíguez, M. Estrada, A. Cerdeira, 2006 .

Considerations on IDDQ test on OTFT circuits

A. Cerdeira, R. Picos, M. Roca, 2012, 2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS).

Conduction mechanisms of silicon oxide/titanium oxide MOS stack structures

Antonio Cerdeira, Benjamín Iñíguez, Magali Estrada, 2008, Microelectron. Reliab..

Analysis and simulation of the post-breakdown leakage current in electrically stressed TiO2/SiO2 gate stacks

E. Miranda, M. Estrada, A. Cerdeira, 2009 .

MOS transistor pressure sensor

A. Cerdeira, G. Romero-Paredes, S. Alcántara, 1998, Proceedings of the 1998 Second IEEE International Caracas Conference on Devices, Circuits and Systems. ICCDCS 98. On the 70th Anniversary of the MOSFET and 50th of the BJT. (Cat. No.98TH8350).