Soo-Young Oh

发表

Fast Generation of Statistically- ase Modeli~~ of On-Chip Interconnect

Norman Chang, Valery Kanevsky, Sam Nakagawa, 1997 .

Examples of Parasitic Elements Simulation

Soo-Young Oh, John L. Moll, Kit Man Cham, 1988 .

A method of computer-aided design for multi-layer technologies compounds

Keh-Jeng Chang, Soo-Young Oh, Keunmyung Lee, 1993 .

Using a statistical metrology framework to identify systematic and random sources of die- and wafer-level ILD thickness variation in CMP processes

Duane S. Boning, J. E. Chung, Keh-Jeng Chang, 1995, Proceedings of International Electron Devices Meeting.

Methodology in Computer-Aided Design for Process and Device Development

Soo-Young Oh, John L. Moll, Kit Man Cham, 1988 .

SUPREM III Application

Soo-Young Oh, John L. Moll, Kit Man Cham, 1988 .

Interconnect modeling for VLSIs

Won-Young Jung, Keun-Ho Lee, Jeong-Taek Kong, 1999, 1999 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD'99 (IEEE Cat. No.99TH8387).

Interconnect modeling and design in high-speed VLSI/ULSI systems

Ken Lee, Keh-Jeng Chang, Norman Chang, 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

A New Field-Dependent Mobility Model Based on a New Effective Field and Universal Mobility Relations

Soo-Young Oh, Soo-Young Oh, Soo-Young Oh, 1990 .

2001 needs for multi-level interconnect technology

Keh-Jeng Chang, Soo-Young Oh, Keh-Jeng Chang, 1995 .

Parameterized SPICE subcircuits for multilevel interconnect modeling and simulation

Keh-Jeng Chang, Soo-Young Oh, Norman H. Chang, 1992 .

HIVE: an efficient interconnect capacitance extractor to support submicron multilevel interconnect designs

Ken Lee, Keh-Jeng Chang, Soo-Young Oh, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

Numerical Simulation Systems

Soo-Young Oh, John L. Moll, Kit Man Cham, 1988 .

INTEGRATED ENVIRONMENT FOR HIGH-SPEED INTERCONNECT MODELING

Soo-Young Oh, Ken Lee, Kent Okasaki, 1989 .

An indirect extraction of interconnect technology parameters for efficient statistical interconnect modeling and its applications

Won-Young Jung, Keun-Ho Lee, Young-Kwan Park, 2000, 2000 5th International Workshop on Statistical Metrology (Cat.No.00TH8489.

Analytical Model and Numerical Simulation of High Level Injection in Si / SiGe HBTs

Soo-Young Oh, Robert W. Dutton, Paul Vande Voorde, 1991 .

Parasitic Elements Simulation

Soo-Young Oh, John L. Moll, Kit Man Cham, 1988 .

Interconnect modeling in deep submicron design

Won-Young Jung, Keun-Ho Lee, Jeong-Taek Kong, 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

Technological limitations in submicron on-chip interconnect

Ken Lee, Keh-Jeng Chang, Soo-Young Oh, 1993, Other Conferences.

IPDA: interconnect performance design assistant

Ken Lee, Keh-Jeng Chang, Soo-Young Oh, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Fast generation of statistically-based worst-case modeling of on-chip interconnect

Norman Chang, Khalid Rahmat, Soo-Young Oh, 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

Introduction to Numerical Simulation System

Soo-Young Oh, John L. Moll, Kit Man Cham, 1986 .

An Integrated Environment for Electrical Modeling and Characterization of Packages and Interconnects in High-Speed VLSI System

Soo-Young Oh, Soo-Young Oh, 1990 .

A scaling scheme and optimization methodology for deep sub-micron interconnect

J. Moll, Khalid Rahmat, Soo-Young Oh, 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

Physical and technological limitations and their optimization in submicron ULSI interconnect

Soo-Young Oh, John L. Moll, Keh Jeng Chang, 1991, 1991 Proceedings Eighth International IEEE VLSI Multilevel Interconnection Conference.

Basic Techniques in Simulations for Advanced Process Development

Soo-Young Oh, John L. Moll, Kit Man Cham, 1986 .

Nondestructive Multilevel Interconnect Parameter Characterization For High-performance Manufacturable VLSI Technologies

Keh-Jeng Chang, Soo-Young Oh, Norman H. Chang, 1993, Symposium 1993 on VLSI Technology.

Optimization of Interconnect Geometry for High-Performance Microprocessors

Khalid Rahmat, Soo-Young Oh, 1997 .

Transient analysis of MOS transistors

Soo-Young Oh, Robert W. Dutton, D. E. Ward, 1980 .

Statistical metrology for interlevel dielectric thickness variation

Duane S. Boning, J. E. Chung, Keh-Jeng Chang, 1994, Advanced Lithography.

Parameterized SPICE subcircuits for submicron multilevel interconnect modeling

Keh-Jeng Chang, Soo-Young Oh, Keunmyung Lee, 1992, 1992 Symposium on VLSI Technology Digest of Technical Papers.

A scaling scheme for interconnect in deep-submicron processes

Soo-Young Oh, W. T. Lynch, O. S. Nakagawa, 1995, Proceedings of International Electron Devices Meeting.

EFFECT OF FINE-LINE DENSITY AND PITCH ON INTERCONNECT ILD THICKNESS VARIATION IN OXIDE CMP PROCESSES

Duane S. Boning, Soo-Young Oh, B. E. Stine, 1997 .

A Novel Statistical Metrology Framework for Identifying Sources of Variation in Oxide Chemical‐Mechanical Polishing

Duane S. Boning, Hitoshi Aoki, Soo-Young Oh, 1998 .

A simplified two-dimensional numerical analysis of MOS devices including transient phenomena

Soo-Young Oh, 1981 .