P. Chang

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Eecient Instruction Sequencing with Inline Target Insertion 1

W. Hwu, M. Ieee, P. Chang, 1990 .

IIC FILE COO 1 U " U-ENG-0-IS COORDINATED SCIENCE LABORATORY Colleg of Enginfteiu ADA 222 807 EFFICIENT INSTRUCTION SEQUENCING WITH INLINE TARGET INSERTION

W. Hwu, P. Chang, Pohua, 2022 .

Exploiting parallel microprocessor microarchitectures with a compiler code generator

W. Hwu, P. Chang, 1988, [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings.

IMPACT: an architectural framework for multiple-instruction-issue processors

Wen-mei W. Hwu, W.Y. Chen, W.W. Hwu, 1991, [1991] Proceedings. The 18th Annual International Symposium on Computer Architecture.

Scalar program performance on multiple-instruction-issue processors with a limited number of registers

Scott Mahlke, Pohua P. Chang, William Y. Chen, 1992, Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences.

for Reliable and High-Performance ComputingUniversity of IllinoisUrbana , IL 61801

S. Mahlke, W. Hwu, William Y. Chen, 1992 .

Memory Optimizations in the Intel Reference Compiler

K. Sridharan, Utpal Banerjee, Pohua P. Chang, 1996, LCPC.

Using profile information to assist classic code optimizations

Scott A. Mahlke, Wen-mei W. Hwu, Pohua P. Chang, 1991, Softw. Pract. Exp..

Inline function expansion for compiling C programs

Wen-mei W. Hwu, Pohua P. Chang, W. Hwu, 1989, PLDI '89.

Achieving High Instruction Cache Performance With An Optimizing Compiler

Wen-mei W. Hwu, Pohua P. Chang, W. Hwu, 1989, The 16th Annual International Symposium on Computer Architecture.

Trace Selection For Compiling Large C Application Programs To Microcode

Wen-mei W. Hwu, Pohua P. Chang, W. Hwu, 1988, [1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21.

The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors

Scott A. Mahlke, Wen-mei W. Hwu, Daniel M. Lavery, 1995, IEEE Trans. Computers.

Comparing Software And Hardware Schemes For Reducing The Cost Of Branches

Thomas M. Conte, Wen-mei W. Hwu, Pohua P. Chang, 1989, The 16th Annual International Symposium on Computer Architecture.

The Effect of Code Expanding Optimizations on Instruction Cache Design

Thomas M. Conte, Wen-mei W. Hwu, Pohua P. Chang, 1993, IEEE Trans. Computers.

The superblock: An effective technique for VLIW and superscalar compilation

Scott A. Mahlke, Richard E. Hank, Roger A. Bringmann, 1993, The Journal of Supercomputing.

Three Architecutral Models for Compiler-Controlled Speculative Execution

Scott A. Mahlke, Wen-mei W. Hwu, Nancy J. Warter, 1995, IEEE Trans. Computers.

Data access microarchitectures for superscalar processors with compiler-assisted data prefetching

Scott A. Mahlke, Wen-mei W. Hwu, Pohua P. Chang, 1991, MICRO 24.

Using Predicated Execution to Improve the Performance of a Dynamically Scheduled Machine with Speculative Execution

Yale N. Patt, Pohua P. Chang, Eric Hao, 1995, International Journal of Parallel Programming.

Integrating Program Optimizations and Transformations with the Scheduling of Instruction Level Parallelism

Rajiv Gupta, Mary Lou Soffa, Pohua P. Chang, 1996, LCPC.

Profile‐guided automatic inline expansion for C programs

Scott A. Mahlke, Wen-mei W. Hwu, Pohua P. Chang, 1992, Softw. Pract. Exp..

Three-dimensional eye-head coordination after injection of muscimol into the interstitial nucleus of Cajal (INC).

Hongying Wang, J Douglas Crawford, Eliana M Klier, 2007, Journal of neurophysiology.

Integer Loop Code Generation for VLIW

Utpal Banerjee, Pohua P. Chang, James Radigan, 1995, LCPC.

Comparing static and dynamic code scheduling for multiple-instruction-issue processors

Scott A. Mahlke, Wen-mei W. Hwu, Pohua P. Chang, 1991, MICRO 24.

Bidirectional Scheduling: A New Global Code Scheduling Approach

Utpal Banerjee, Pohua P. Chang, Youfeng Wu, 1996, LCPC.

Tolerating data access latency with register preloading

Scott A. Mahlke, Wen-mei W. Hwu, Tokuzo Kiyohara, 1992, ICS '92.