Prasenjit Biswas

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A Hybrid Architecture and Adaptive Scheduling for Parallel Execution of Logic Programs

Surapong Auwatanamongkol, Prasenjit Biswas, S. Auwatanamongkol, 1991, ICPP.

A supervised learning algorithm for hierarchical classification of fuzzy patterns

Arun K. Majumdar, Prasenjit Biswas, 1983, Inf. Sci..

REDEFINE: Runtime reconfigurable polymorphic ASIC

S. K. Nandy, Ranjani Narayan, Alexander Fell, 2009, TECS.

A fuzzy hybrid model for pattern classification with application to recognition of handprinted devanagari

Prasenjit Biswas, 1980 .

Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform

S. K. Nandy, Ranjani Narayan, Prasenjit Biswas, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

SH-5: The 64-Bit SuperH Architecture

Yasuhiko Saito, Fumio Arakawa, Kunio Uchiyama, 2000, IEEE Micro.

Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT

S. K. Nandy, Ranjani Narayan, Alexander Fell, 2009, 2009 IEEE International SOC Conference (SOCC).

Hardware Consolidation Of Systolic Algorithms On A Coarse Grained Runtime Reconfigurable Architecture

Prasenjit Biswas, 2011 .

A Fuzzy Hybrid Model for Pattern Classification

Arun K. Majumdar, Prasenjit Biswas, A. Majumdar, 1988, Pattern Recognition.

A demand-driven macro-dataflow schema for distributed graph reduction on multiple G-machines

Jin Chen, Prasenjit Biswas, P. Biswas, 1990, Microprocessing and Microprogramming.

A snooping cache coherency protocol for hierarchically organized multiprocessors

Prasenjit Biswas, Gautam Dewan, 1991 .

PARSA: A Parallel Program Scheduling and Assessment Environment

Krishna M. Kavi, Ali R. Hurson, Behrooz Shirazi, 1993, 1993 International Conference on Parallel Processing - ICPP'93.

LogDf: A Data-Driven Abstract Machine Model for Parallel Execution of Logic Programs

Chien-Chao Tseng, Prasenjit Biswas, 1988, FGCS.

Functional verification of the superscalar SH-4 microprocessor

Norio Nakagawa, Kunio Uchiyama, Prasenjit Biswas, 1997, Proceedings IEEE COMPCON 97. Digest of Papers.

Book review: The Art of Computer Systems Performance Analysis - by Raj Jain (ISBN 0471-50336-3, 1991, 685 pages, Price: $ 52.95 John Wiley & Sons Inc., New York)

Prasenjit Biswas, 1991, SIGM.

A Data-Driven Parallel Execution Model for Logic Programs

Chien-Chao Tseng, Prasenjit Biswas, 1988, ICLP/SLP.

SH3: high code density, low power

Ikuya Kawasaki, Shinichi Yoshioka, Prasenjit Biswas, 1995, IEEE Micro.

Architectural support for variable addressing in Ada— A design approach

Subrata Dasgupta, Prasenjit Biswas, 2004, International Journal of Computer & Information Sciences.

A Scalable Abstract Machine Model to Support Limited-OR (LOR) / Restricted-AND Parallelism (RAP) in Logic Programs

David Y. Y. Yun, Prasenjit Biswas, Shyh-Chang Su, 1988, ICLP/SLP.

Abstract machine LORAP II and experiments in process grain size determination for parallel execution of logic programs

Prasenjit Biswas, Chin-Feng Fan, 1989, [Proceedings 1989] IEEE International Workshop on Tools for Artificial Intelligence.

Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra

D. M. H. Walker, Prasenjit Biswas, D. Walker, 2017, 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID).

Streaming FFT on REDEFINE-v2: an application-architecture design space exploration

S. K. Nandy, Ranjani Narayan, Alexander Fell, 2009, CASES '09.

Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform

S. K. Nandy, Ranjani Narayan, Prasenjit Biswas, 2010, 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.

An abstract machine model for multiprocessor implementation of logic programs

Prasenjit Biswas, Shyh-Chang Su, 1988 .

A Mathematical Framework for Exploring Protein Folding Dynamics using Probabilistic Model Checking

Sarit Pal, Prasenjit Biswas, Sunil Khatri, 2020, 2020 3rd International Conference on Information and Computer Technologies (ICICT).

Cut and side-effects in a data-driven implementation of Prolog

Surapong Auwatanamongkol, Andrzej Ciepielewski, Prasenjit Biswas, 1994, New Generation Computing.

An extended scheduling technique for software pipelining

Prasenjit Biswas, Dagung Lu, 1993, Microprocess. Microprogramming.

Scheduling demand-driven parallel logic programs on transputers

Prasenjit Biswas, Shyh-Chang Su, 1990 .

Hardware implementation of 4×4 DCT/quantization block using multiplication and error-free algorithm

K. Rajan, Prasenjit Biswas, Suvam Nandi, 2009, TENCON 2009 - 2009 IEEE Region 10 Conference.