Kazutoshi Kobayashi

发表

Radiation-Hardened Flip-Flops With Low-Delay Overhead Using pMOS Pass-Transistors to Suppress SET Pulses in a 65-nm FDSOI Process

Kazutoshi Kobayashi, Jun Furuta, Kodai Yamada, 2018, IEEE Transactions on Nuclear Science.

Initial and long-term frequency degradation of ring oscillators caused by plasma-induced damage in 65 nm bulk and fully depleted silicon-on-insulator processes

Kazutoshi Kobayashi, Ryo Kishida, Azusa Oshima, 2015 .

Evaluation of plasma-induced damage and bias temperature instability depending on type of antenna layer using current-starved ring oscillators

J. Furuta, Kazutoshi Kobayashi, Ryo Kishida, 2018 .

A low surge voltage and fast speed gate driver for SiC MOSFET with switched capacitor circuit

J. Furuta, Kazutoshi Kobayashi, Fei Mo, 2016, 2016 IEEE 4th Workshop on Wide Bandgap Power Devices and Applications (WiPDA).

A 65 nm Complementary Metal--Oxide--Semiconductor 400 ns Measurement Delay Negative-Bias-Temperature-Instability Recovery Sensor with Minimum Assist Circuit

H. Onodera, Kazutoshi Kobayashi, H. Makino, 2011 .

Multicore Large-Scale Integration Lifetime Extension by Negative Bias Temperature Instability Recovery-Based Self-Healing

Kazutoshi Kobayashi, Hidetoshi Onodera, Hiroaki Makino, 2012 .

A 1 MHz Boost DC-DC Converter with Turn on ZCS Capability to Reduce EMI

J. Furuta, Kazutoshi Kobayashi, H. Yoshioka, 2020, 2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia).

Random Telegraph Noise Under Switching Operation

Kazutoshi Kobayashi, Ryo Kishida, Takashi Matsumoto, 2020 .

Extracting Voltage Dependence of BTI-induced Degradation Without Temporal Factors by Using BTI-Sensitive and BTI-Insensitive Ring Oscillators

J. Furuta, Kazutoshi Kobayashi, Ryo Kishida, 2020, IEEE Transactions on Semiconductor Manufacturing.

A Low-Power High-Performance Vector-Pipeline DSP for Low-Rate Videophones

Hidetoshi Onodera, Kosuke Takai, Xiang Li, 2001 .

Higher-Order Effect of Source–Drain Series Resistance on Saturation Drain Current in Sub-20 nm Metal–Oxide–Semiconductor Field-Effect Transistors

A. Hiroki, Kazutoshi Kobayashi, J. Yoon, 2012 .

Capacitor-Based Three-Level Gate Driver for GaN HEMT Only with a Single Voltage Supply

J. Furuta, Kazutoshi Kobayashi, J. Nagao, 2020, 2020 IEEE 21st Workshop on Control and Modeling for Power Electronics (COMPEL).

Analysis of Soft Error Rates in 65- and 28-nm FD-SOI Processes Depending on BOX Region Thickness and Body Bias by Monte-Carlo Based Simulations

Kazutoshi Kobayashi, Jun Furuta, Junki Yamaguchi, 2016, IEEE Transactions on Nuclear Science.

Analysis of BOX Layer Thickness on SERs of 65 and 28nm FD-SOI Processes by a Monte-Carlo Based Simulation Tool

J. Furuta, S. Kanda, Kazutoshi Kobayashi, 2015, 2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

Impact of Body-Biasing Technique on RTN-induced Delay Fluctuation

T. Matsumoto, H. Onodera, Kazutoshi Kobayashi, 2012 .

Variability Characterization Using an RO-array Test Structure and Its Impact on Design

Kazutoshi Kobayashi, Hidetoshi Onodera, Shinichi Nishizawa, 2010 .

Physical insights on imprint and application to functional memory with ferroelectric materials

Kazutoshi Kobayashi, K. Tamaru, H. Nozawa, 2001 .

Special section on VLSI design technology in the sub-100 nm era

Makoto Nagata, Akira Matsuzawa, Mototsugu Hamada, 2006 .

Memory based architecture and its implementation scheme named bit-parallel block-parallel functional memory type parallel processor BPBP FMPP

Kazutoshi Kobayashi, Hidetoshi Onodera, Keikichi Tamaru, 1998 .

Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process

Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi, 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Radiation-Hardened Structure to Reduce Sensitive Range of a Stacked Structure for FDSOI

Kazutoshi Kobayashi, Jun Furuta, Kodai Yamada, 2019, IEEE Transactions on Nuclear Science.

Process Dependence of Soft Errors Induced by Alpha Particles, Heavy Ions, and High Energy Neutrons on Flip Flops in FDSOI

Kazutoshi Kobayashi, Jun Furuta, Kodai Yamada, 2019, IEEE Journal of the Electron Devices Society.

Radiation-Hardened Flip-Flops with Small Area and Delay Overheads Using Guard-Gates in FDSOI Processes

J. Furuta, Kodai Yamada, Kazutoshi Kobayashi, 2018, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process

Kazutoshi Kobayashi, Jun Furuta, Masashi Hifumi, 2018, IEICE Trans. Electron..

Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process

Kazutoshi Kobayashi, Jun Furuta, Kodai Yamada, 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

Evaluation of Soft Error Tolerance on Flip-Flops Restoring from a Single Node Upset by C-elements

J. Furuta, Kazutoshi Kobayashi, Ryuichi Nakajima, 2022, 2022 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK).

Radiation Hardened Flip-Flops Minimizing Area, Power, and Delay Overheads with 1/100 Lower α-SER in a 130 nm Bulk Process

J. Furuta, Kazutoshi Kobayashi, Ryuichi Nakajima, 2022, 2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Soft-error Tolerance by Guard-Gate Structures on Flip-Flops in 22/65 nm FD-SOI Technologies

J. Furuta, Kazutoshi Kobayashi, Ryuichi Nakajima, 2022 .

Intrinsic Vulnerability to Soft Errors and a Mitigation Technique by Layout Optimization on DICE Flip Flops in a 65-nm Bulk Process

Kazutoshi Kobayashi, Jun Furuta, Yuto Tsukita, 2021, IEEE Transactions on Nuclear Science.

Evaluation of Soft-Error Tolerance by Neutrons and Heavy Ions on Flip Flops With Guard Gates in a 65-nm Thin BOX FDSOI Process

Kazutoshi Kobayashi, Jun Furuta, Kodai Yamada, 2020, IEEE Transactions on Nuclear Science.

Soft-Error Tolerance Depending on Supply Voltage by Heavy Ions on Radiation-Hardened Flip Flops in a 65 nm Bulk Process

Jun Furuta, Kazutoshi Kobayashi, Yuto Tsukita, 2019, 2019 IEEE 13th International Conference on ASIC (ASICON).

A non-redundant low-power flip flop with stacked transistors in a 65 nm thin BOX FDSOI process

Kazutoshi Kobayashi, Jun Furuta, Masashi Hifumi, 2016, 2016 16th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

Impact of Drive Strength and Well-contact Density on Heavy-ion-induced Single Event Transient

M. Masuda, Kazutoshi Kobayashi, K. Takeuchi, 2013 .

A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop DICE ACFF

Kazutoshi Kobayashi, Kanto Kubota, Masaki Masuda, 2012 .

An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity

Kazutoshi Kobayashi, Hidetoshi Onodera, Jun Furuta, 2010, IEICE Trans. Electron..

Characterizing SRAM and FF soft error rates with measurement and simulation

Masanori Hashimoto, Kazutoshi Kobayashi, Jun Furuta, 2019, Integr..

A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop capable of protecting soft errors on the C-element

Kazutoshi Kobayashi, Hidetoshi Onodera, Jun Furuta, 2010, 2010 Symposium on VLSI Circuits.

Compact Modeling of NBTI Replicating AC Stress / Recovery from a Single-shot Long-term DC Measurement

Takashi Matsumoto, Shinichi Nishizawa, Kazutoshi Kobayashi, 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement

Ryo Kishida, Kazutoshi Kobayashi, Takumi Hosaka, 2020, IPSJ Trans. Syst. LSI Des. Methodol..

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Hideharu Amano, Kazutoshi Kobayashi, Kimiyoshi Usami, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Hideharu Amano, Duc-Hung Le, Cong-Kha Pham, 2014, 2014 IEEE COOL Chips XVII.

Highly-reliable integrated circuits for Gro

Kazutoshi Kobayash, Kazutoshi Kobayashi, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

Radiation-Induced Soft Errors

Shusuke Yoshimoto, Hiroshi Kawaguchi, Yukio Mitsuyama, 2018, VLSI Design and Test for Systems Dependability.

A yield and speed enhancement scheme under within-die variations on 90nm LUT array

Kazutoshi Kobayashi, Hidetoshi Onodera, Manabu Kotani, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing

K. Nii, Kazutoshi Kobayashi, Yoshisato Yokoyama, 2023, IEEE Journal of Solid-State Circuits.

Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs

Koji Nii, Kazutoshi Kobayashi, Yuichiro Ishii, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Degradation caused by Negative Bias temperature instability depending on Body Bias on NMOS or PMOS in 65 nm bulk and thin-BOX FDSOI processes

Kazutoshi Kobayashi, Ryo Kishida, 2017, IEEE Electron Devices Technology and Manufacturing Conference.

An Asynchronous Buck Converter by Using a Monolithic GaN IC Integrated by an Enhancement-Mode GaN-on-SOI Process

J. Furuta, Kazutoshi Kobayashi, J. Nagao, 2021, 2021 IEEE 8th Workshop on Wide Bandgap Power Devices and Applications (WiPDA).

Bias Temperature Instability Depending on Body Bias through Buried Oxide (BOX) Layer in a 65 nm Fully-Depleted Silicon-On-Insulator Process

Kazutoshi Kobayashi, Ryo Kishida, Ikuo Suda, 2021, 2021 IEEE International Reliability Physics Symposium (IRPS).

Dependence of Cell Distance and Well-Contact Density on MCU Rates by Device Simulations and Neutron Experiments in a 65-nm Bulk Process

Kazutoshi Kobayashi, Hidetoshi Onodera, Jun Furuta, 2014, IEEE Transactions on Nuclear Science.

Impact of body bias on soft error tolerance of bulk and Silicon on Thin BOX structure in 65-nm process

Kazutoshi Kobayashi, Kuiyuan Zhang, Kazutoshi Kobayashi, 2014, 2014 IEEE International Reliability Physics Symposium.

Physical-based RTN modeling of ring oscillators in 40-nm SiON and 28-nm HKMG by bimodal defect-centric behaviors

Kazutoshi Kobayashi, Hidetoshi Onodera, Takashi Matsumoto, 2016, 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era

Kazutoshi Kobayashi, Hidetoshi Onodera, Masao Aramoto, 2005, IEICE Trans. Electron..

A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing

H. Onodera, K. Kobayashi, M. Aramoto, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

A vector-pipeline DSP for low-rate videophones

Xiang Li, Kazutoshi Kobayashi, Hidetoshi Onodera, 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

Impact of RTN and NBTI on Synchronous Circuit Reliability

H. Onodera, Kazutoshi Kobayashi, Takashi Matsumoto, 2011 .

Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells

Kazutoshi Kobayashi, Hidetoshi Onodera, Akira Tsuchiya, 2010, IPSJ Trans. Syst. LSI Des. Methodol..

NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures

Kazutoshi Kobayashi, Michitarou Yabuuchi, Kazutoshi Kobayashi, 2012, IPSJ Trans. Syst. LSI Des. Methodol..