Maolin Guan

Load scheduling: Reducing pressure on distributed register files for free

Nan Wu, Mei Wen, Chunyuan Zhang, 2008, 2008 Asia and South Pacific Design Automation Conference.

Register File Load Balanced VLIW Scheduling for Distributed Register Files

Nan Wu, Chunyuan Zhang, Maolin Guan, 2013 .

An Energy-Efficient Processor Core for Massively Parallel Computing

Jun Cai, Nan Wu, Chunyuan Zhang, 2012, 2012 International Conference on Computer Science and Service System.

Tiled Multi-Core Stream Architecture

Yi He, Nan Wu, Ju Ren, 2011, Trans. High Perform. Embed. Archit. Compil..

Fully Distributed On-chip Instruction Memory Design for Stream Architecture Based on Field-Divided VLIW Compression

Yi He, Chunyuan Zhang, Tian Tian, 2012, 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems.

On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator

Wei Wu, Yi He, Nan Wu, 2008, IEEE Micro.

Software integration of identical DLP threads via compilation for VLIW processors

Nan Wu, Mei Wen, Chunyuan Zhang, 2010, 5th International Conference on Computer Sciences and Convergence Information Technology.