K. Masselos

发表

AMDREL: On Designing Reconfigurable Embedded Structures for the Future Reconfigurable SoC for Wireless Communication Applications

K. Tatas, D. Soudris, S. Siskos, 2002 .

Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework

Qiang Liu, Peter Y. K. Cheung, George A. Constantinides, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Data Reuse Exploration under Area Constraints for Low Power Reconfigurable Systems

G. Constantinides, P. Cheung, K. Masselos, 2007 .

Outer Loop Pipelining for Application Specific Datapaths in FPGAs

Peter Y. K. Cheung, Kostas Masselos, Kieron Turkington, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A novel methodology for power consumption reduction in a class of DSP algorithms

Thanos Stouraitis, Kostas Masselos, Constantinos E. Goutis, 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

Novel vector quantization based algorithms for low-power image coding and decoding

T. Stouraitis, K. Masselos, C. Goutis, 1999 .

Prototyping of a WLAN system using C++ based architecture exploration

N. Voros, K. Masselos, 2007, MobiMedia '07.

Realization of wireless multimedia communication systems on reconfigurable platforms

Kostas Masselos, Spyros Blionas, Antti Pelkonen, 2003, J. Syst. Archit..

A HIPERLAN/2 - IEEE 802.11a Reconfigurable System-on-Chip

Kostas Masselos, Chrissavgi Dre, Christos Drosos, 2002, FPL.

A MATLAB Vectorizing Compiler Targeting Application-Specific Instruction Set Processors

Karthick Parashar, Francky Catthoor, Kostas Masselos, 2017, ACM Trans. Design Autom. Electr. Syst..

FSMD-Based Hardware Accelerators for FPGAs

Kostas Masselos, Nikolaos Kavvadias, Vasiliki Giannakopoulou, 2012 .

Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform

Dimitrios Soudris, Kostas Masselos, Spiridon Nikolaidis, 2004, PATMOS.

A reusable IP FFT core for DSP applications

Dimitrios Soudris, Kostas Masselos, Adonios Thanailakis, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Strategy for power efficient combined task and data parallelism exploration illustrated on a QSDPCM video codec

Hugo De Man, Francky Catthoor, Kostas Masselos, 1999, J. Syst. Archit..

An early memory hierarchy evaluation simulator for multimedia applications

Kostas Masselos, Grigoris Dimitroulakos, Theodoros Lioris, 2014, Microprocess. Microsystems.

Automated Synthesis of FSMD-Based Accelerators for Hardware Compilation

Kostas Masselos, Nikolaos Kavvadias, K. Masselos, 2012, 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors.

A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints

Hugo De Man, Francky Catthoor, Constantinos E. Goutis, 2000, J. VLSI Signal Process..

Reuse distance analysis for locality optimization in loop-dominated applications

Kostas Masselos, Grigoris Dimitroulakos, Christakis Lezos, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation

Kostas Masselos, Grigoris Dimitroulakos, Theodoros Lioris, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Automatic On-chip Memory Minimization for Data Reuse

Qiang Liu, Peter Y. K. Cheung, George A. Constantinides, 2007, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007).

A Locality Optimizer for Loop-dominated Applications Based on Reuse Distance Analysis

Konstantinos Masselos, Ioannis Latifis, Christakis Lezos, 2020, ACM Trans. Design Autom. Electr. Syst..

A parallel image compression scheme based on fractal coding and vector quantization

Thanos Stouraitis, Kostas Masselos, K. Karagianni, 1996, Proceedings of Third International Conference on Electronics, Circuits, and Systems.

Implementation of Wireless Communications Systems on FPGA-Based Platforms

Kostas Masselos, Nikos S. Voros, N. Voros, 2007, EURASIP J. Embed. Syst..

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems

Qiang Liu, Peter Y. K. Cheung, George A. Constantinides, 2009, IET Comput. Digit. Tech..

Effect of data transfer and storage optimization on design quality factors of multimedia algorithms realized on instruction set processors

Francky Catthoor, Kostas Masselos, Constantinos E. Goutis, 2001 .

Low-power implementation of discrete wavelet transform

Thanos Stouraitis, Constantinos E. Goutis, Kostas Masselos, 1998, 9th European Signal Processing Conference (EUSIPCO 1998).

Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs

Maria E. Angelopoulou, Peter Y. K. Cheung, Kostas Masselos, 2008, J. Signal Process. Syst..