Alexander V. Veidenbaum

发表

Dynamically adaptive fetch size prediction for data caches

Weiyu Tang, Alexander V. Veidenbaum, Alexandru Nicolau, 2003, Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003.

Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements

Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau, 2007, PARCO.

Guest Editor's Introduction

Alexander V. Veidenbaum, 2004, International Journal of Parallel Programming.

Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® Core™ 2 Duo processor

Milind Girkar, Xinmin Tian, Alexander V. Veidenbaum, 2008, 2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation.

Low Energy Associative Data Caches for Embedded Systems

Alexander V. Veidenbaum, Dan Nicolaescu, Alex Nicolau, 2003, Embedded Software for SoC.

OpenCV.js: computer vision processing for the open web platform

Alexander V. Veidenbaum, Alexandru Nicolau, Mohammad R. Haghighat, 2018, MMSys.

A Simple Low-Energy Instruction Wakeup Mechanism

Mateo Valero, Alexander V. Veidenbaum, Adrián Cristal, 2003, ISHPC.

Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption

Rajesh K. Gupta, Weiyu Tang, Alexander V. Veidenbaum, 2002, ISHPC.

Scalability of the Cedar system

Alexander V. Veidenbaum, Stephen W. Turner, 1994, Proceedings of Supercomputing '94.

Cache with Adaptive Fetch Size

Rajesh Gupta, Weiyu Tang, Alexander V. Veidenbaum, 2000 .

Compiler-Directed Cache Assist Adaptivity

Rajesh K. Gupta, Alexander V. Veidenbaum, Alexandru Nicolau, 2000, ISHPC.

A distributed processor state management architecture for large-window processors

Mateo Valero, Alexander V. Veidenbaum, Adrián Cristal, 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

The Performance of Software-managed Multiprocessor Caches on Parallel Numerical Programs

Alexander V. Veidenbaum, Hoichi Cheong, 1987, ICS.

Preliminary basic performance analysis of the Cedar multiprocessor memory system

Alexander V. Veidenbaum, William Jalby, Kyle A. Gallivan, 1991 .

On leakage power optimization in clock tree networks for ASICs and general-purpose processors

Houman Homayoun, Fadi J. Kurdahi, Alexander V. Veidenbaum, 2011, Sustain. Comput. Informatics Syst..

Using a Way Cache to Improve Performance of Set-Associative Caches

Alexander V. Veidenbaum, Alexandru Nicolau, Dan Nicolaescu, 2005, ISHPC.

Dynamic-vector execution on a general purpose EDGE chip multiprocessor

Mateo Valero, Osman S. Unsal, Alexander V. Veidenbaum, 2014, 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).

Special issue on energy efficient multi-core and many-core systems, Part II

Hannu Tenhunen, Pasi Liljeberg, Alexander V. Veidenbaum, 2017, J. Parallel Distributed Comput..

An asymmetric clustered processor based on value content

Mateo Valero, Alexander V. Veidenbaum, Adrián Cristal, 2005, ICS '05.

A fault tolerant self-scheduling scheme for parallel loops on shared memory systems

Alexander V. Veidenbaum, Alexandru Nicolau, Yizhuo Wang, 2012, 2012 19th International Conference on High Performance Computing.

Multiple stream tracker: a new hardware stride prefetcher

Alexander V. Veidenbaum, Taesu Kim, Dali Zhao, 2014, Conf. Computing Frontiers.

Reducing data cache energy consumption via cached load/store queue

Alexander V. Veidenbaum, Alexandru Nicolau, Dan Nicolaescu, 2003, ISLPED '03.

Line size adaptivity analysis of parameterized loop nests for direct mapped data cache

Rajesh K. Gupta, Alexander V. Veidenbaum, Alexandru Nicolau, 2005, IEEE Transactions on Computers.

Improving SDRAM access energy efficiency for low-power embedded systems

Alexander V. Veidenbaum, Arun Kejariwal, Jelena Trajkovic, 2008, TECS.

Comparison and analysis of software and directory coherence schemes

Alexander V. Veidenbaum, Yung-Chin Chen, 1991, Proceedings of the 1991 ACM/IEEE Conference on Supercomputing (Supercomputing '91).

Optimizing Program Performance via Similarity, Using Feature-aware and Feature-agnostic Characterization Approaches

Alexander V. Veidenbaum, Alexandru Nicolau, Nikil Dutt, 2013 .

Design and Analysis of a Scalable, Shared-memory System with Support for Burst Traffic *

Alexander V. Veidenbaum, Elana D. Granston, Stephen W. Turner, 1992 .

A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors

Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau, 2009, Neural Networks.

Revisiting level-0 caches in embedded processors

Alexander V. Veidenbaum, Taesu Kim, Dali Zhao, 2012, CASES '12.

An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors1

Alexander V. Veidenbaum, Edward H. Gornish, 2004, International Journal of Parallel Programming.

Guest Editors' Introduction: Application-Specific Microprocessors

Alexander V. Veidenbaum, Alex Orailoglu, 2003, IEEE Des. Test Comput..

COPPER: COMPILER-CONTROLLED ON-DEMAND APPROACH TO POWER-EFFICIENT COMPUTING

Rajesh Gupta, Alexander V. Veidenbaum, Nikil Dutt, 2003 .

Caching values in the load store queue

Alexander V. Veidenbaum, Alexandru Nicolau, Dan Nicolaescu, 2004, The IEEE Computer Society's 12th Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, 2004. (MASCOTS 2004). Proceedings..

Impact of JVM superoperators on energy consumption in resource-constrained embedded systems

Alexander V. Veidenbaum, Alexandru Nicolau, Carmen Badea, 2008, LCTES '08.

Energy-Effective Instruction Fetch Unit for Wide Issue Processors

Alexander V. Veidenbaum, Juan L. Aragón, 2005, Asia-Pacific Computer Systems Architecture Conference.

WebRTCbench: a benchmark for performance assessment of webRTC implementations

Alexander V. Veidenbaum, Alexandru Nicolau, Qiang Lu, 2015, 2015 13th IEEE Symposium on Embedded Systems For Real-time Multimedia (ESTIMedia).

Reducing power with an L0 instruction cache using history-based prediction

Weiyu Tang, Alexander V. Veidenbaum, Alexandru Nicolau, 2002, International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems.

An Optimized Front-End Physical Register File with Banking and Writeback Filtering

Mateo Valero, Alexander V. Veidenbaum, Adrián Cristal, 2004, PACS.

Compiler-directed data prefetching in multiprocessors with memory hierarchies

Alexander V. Veidenbaum, Elana D. Granston, Edward H. Gornish, 1990, ICS '90.

Instruction cache power-performance optimization via run-time prediction

Weiyu Tang, Alexander V. Veidenbaum, 2004 .

Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks

Houman Homayoun, Fadi J. Kurdahi, Alexander V. Veidenbaum, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

The Cedar System And An Initial Performance Study

David A. Padua, Rudolf Eigenmann, Alexander V. Veidenbaum, 1993, Proceedings of the 20th Annual International Symposium on Computer Architecture.

Compiler-directed data prefetching in multiprocessors with memory hierarchies

Alexander V. Veidenbaum, Elana D. Granston, Edward H. Gornish, 1990 .

Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy

Alexander V. Veidenbaum, Babak Salamat, Dan Nicolaescu, 2006, 2006 International Conference on Computer Design.

Power-aware load balancing of large scale MPI applications

Mateo Valero, Jesús Labarta, Alexander V. Veidenbaum, 2009, 2009 IEEE International Symposium on Parallel & Distributed Processing.

LORE: A loop repository for the evaluation of compilers

Zhi Chen, Josep Torrellas, David A. Padua, 2017, 2017 IEEE International Symposium on Workload Characterization (IISWC).

A version control approach to Cache coherence

Alexander V. Veidenbaum, Hoichi Cheong, 1989, ICS '89.

SCORE: A Score-Based Memory Cache Replacement Policy

Alexander V. Veidenbaum, Rosario Cammarota, Taesu Kim, 2010 .

Automatic design and optimization of processor data path and memory hierarchy

Daniel D. Gajski, Alexander V. Veidenbaum, Jelena Trajkovic, 2009 .

The effect of restructing compilers on program performance for high-speed computers☆

Alexander V. Veidenbaum, Ron Cytron, David J. Kuck, 1985 .

Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency

Avesta Sasan, Houman Homayoun, Alexander V. Veidenbaum, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Multiple sleep mode leakage control for cache peripheral circuits in embedded processors

Avesta Sasan, Houman Homayoun, Alexander V. Veidenbaum, 2008, CASES '08.

The effect of limited network bandwidth and its utilization by latency hiding techniques in large-scale shared memory systems

Alexander V. Veidenbaum, Sunil Kim, A. Veidenbaum, 1997, Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques.

Large-scale neural circuit mapping data analysis accelerated with the graphical processing unit (GPU)

Alexander V. Veidenbaum, Xiangmin Xu, Alex Nicolau, 2015, Journal of Neuroscience Methods.

EFFECTS OF PROGRAM RESTRUCTURING, ALGORITHM CHANGE, AND ARCHITECTURE CHOICE ON PROGRAM PERFORMANCE.

Alexander V. Veidenbaum, Constantine D. Polychronopoulos, Ron Cytron, 1984 .

Brain Derived Vision Algorithm on High Performance Architectures

Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau, 2009, International Journal of Parallel Programming.

Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management

Avesta Sasan, Houman Homayoun, Alexander V. Veidenbaum, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Decoupled access DRAM architecture

Alexander V. Veidenbaum, Kyle A. Gallivan, 1997, Proceedings Innovative Architecture for Future Generation High-Performance Processors and Systems.

Performance Evaluation of Memory Caches in Multiprocessors

Alexander V. Veidenbaum, Yung-Chin Chen, A. Veidenbaum, 1993, 1993 International Conference on Parallel Processing - ICPP'93.

Preliminary Performance Analysis of the Cedar Multiprocessor Memory System

Alexander V. Veidenbaum, William Jalby, Harry A. G. Wijshoff, 1991, ICPP.

The Organization of the Cedar System

Alexander V. Veidenbaum, Manish Sharma, Edward S. Davidson, 1991, ICPP.

New Opportunities for Compilers in Computer Security

Nahid Farhady Ghalaty, Alexander V. Veidenbaum, Alexandru Nicolau, 2018, LCPC.

Low-power Fetch Unit Desing for Superscalar Processors

Alexander V. Veidenbaum, Juan L. Aragón, 2004 .

SIMD-based soft error detection

Zhi Chen, Alexander V. Veidenbaum, Alexandru Nicolau, 2016, Conf. Computing Frontiers.

A novel architecture for large windows processors

Alexander V. Veidenbaum, Mateo Valero Cortés, Marco Galluzzi, 2007 .

A Compilation and Run-Time Framework for Maximizing Performance of Self-scheduling Algorithms

Alexander V. Veidenbaum, Alexandru Nicolau, Yizhuo Wang, 2014, NPC.

Selective search of inlining vectors for program optimization

Alexander V. Veidenbaum, Alexandru Nicolau, Debora Donato, 2012, CF '12.

Compiler-Directed Cache Line Size Adaptivity

Rajesh K. Gupta, Alexander V. Veidenbaum, Alexandru Nicolau, 2000, Intelligent Memory Systems.

A Data Cache with Dynamic Mapping

Alexander V. Veidenbaum, Alexandru Nicolau, Paolo D'Alberto, 2003, LCPC.

Stale Data Detection and Coherence Enforcement Using Flow Analysis

Alexander V. Veidenbaum, Hoichi Cheong, 1988, ICPP.

Improving Cache Management Policies Using Dynamic Reuse Distances

Mateo Valero, Alexander V. Veidenbaum, Rosario Cammarota, 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

Energy-efficient design for highly associative instruction caches in next-generation embedded processors

Alexander V. Veidenbaum, Juan L. Aragón, Dan Nicolaescu, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Challenges in exploitation of loop parallelism in embedded applications

Milind Girkar, Xinmin Tian, Alexander V. Veidenbaum, 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

Non-Sequential Instruction Cache Prefetching for Multiple-Issue Processors

Alexander V. Veidenbaum, Qingbo Zhao, Abduhl Shameer, 1999, Int. J. High Speed Comput..

A Two-Level Load/Store Queue Based on Execution Locality

Francisco J. Cazorla, Mateo Valero, Alexander V. Veidenbaum, 2008, 2008 International Symposium on Computer Architecture.

A centralized cache miss driven technique to improve processor power dissipation

Avesta Sasan, Houman Homayoun, Alexander V. Veidenbaum, 2008, 2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation.

Performance Characterization of Itanium® 2-Based Montecito Processor

Alexander V. Veidenbaum, Alexandru Nicolau, Arun Kejariwal, 2009, SPEC Benchmark Workshop.

On shortest path routing in single stage shuffle-exchange networks

Alexander V. Veidenbaum, Sunil Kim, A. Veidenbaum, 1995, SPAA '95.

Compiler-assisted, selective out-of-order commit

Alexander V. Veidenbaum, Nam Duong, 2013, IEEE Computer Architecture Letters.

Exploitation of nested thread-level speculative parallelism on multi-core systems

Milind Girkar, Xinmin Tian, Alexander V. Veidenbaum, 2010, CF '10.

Guest Editor's Introduction

Alexander V. Veidenbaum, 2001, International Journal of Parallel Programming.

A software coherence scheme with the assistance of directories

Alexander V. Veidenbaum, Yung-Chin Chen, 1991, ICS '91.

Low energy, highly-associative cache design for embedded processors

Alexander V. Veidenbaum, Dan Nicolaescu, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

MCompiler: A Synergistic Compilation Framework pdf

Alexander V. Veidenbaum, Alexandru Nicolau, Aniket Shivam, 2019, ArXiv.

Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units

Nikil D. Dutt, Avesta Sasan, Houman Homayoun, 2010, CF '10.

High Performance Computing: 5th International Symposium, Ishpc 2003, Tokio-Odaiba, Japan, October 20-22, 2003: Proceedings (LECTURE NOTES IN COMPUTER SCIENCE)

Hideharu Amano, Alexander V. Veidenbaum, Kazuki Joe, 2003 .

Energy aware register file implementation through instruction predecode

Alexander V. Veidenbaum, Marisa López-Vallejo, José Luis Ayala, 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

Temperature aware thread migration in 3D architecture with stacked DRAM

Houman Homayoun, Alexander V. Veidenbaum, Dali Zhao, 2013, International Symposium on Quality Electronic Design (ISQED).

Cache power-performance optimization

Alexander V. Veidenbaum, Dan Nicolaescu, 2006 .

Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009

Alexander V. Veidenbaum, Georgi Gaydadjiev, Carsten Trinitis, 2009, Conf. Computing Frontiers.

Performance of a shared memory system for vector multiprocessors

Alexander V. Veidenbaum, Stephen W. Turner, A. Veidenbaum, 1988, ICS '88.

Author retrospective for compiler-directed data prefetching in multiprocessors with memory hierarchies

Alexander V. Veidenbaum, Elana D. Granston, Eddie Gornish, 2014, ICS 2014.

On the exploitation of loop-level parallelism in embedded applications

Milind Girkar, Xinmin Tian, Alexander V. Veidenbaum, 2009, TECS.

Cache-aware partitioning of multi-dimensional iteration spaces

Alexander V. Veidenbaum, Alexandru Nicolau, Constantine D. Polychronopoulos, 2009, SYSTOR '09.

Special issue on energy efficient multi-core and many-core systems, Part I

Hannu Tenhunen, Pasi Liljeberg, Alexander V. Veidenbaum, 2016, J. Parallel Distributed Comput..

Towards parallelizing the layout engine of firefox

Alexander V. Veidenbaum, Alexandru Nicolau, Mohammad R. Haghighat, 2010 .

Software-directed Cache Management in Multiprocessors

Alexander V. Veidenbaum, Hoichi Cheong, 1990 .

Interconnection network organization and its impact on performance and cost in shared memory multiprocessors

Alexander V. Veidenbaum, Sunil Kim, A. Veidenbaum, 1999, Parallel Comput..

Software fault tolerance for FPUs via vectorization

Zhi Chen, Alexander V. Veidenbaum, Alexandru Nicolau, 2015, 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS).

Compiler optimizations and architecture design issues for multiprocessors (parallel)

Alexander V. Veidenbaum, 1985 .

Power-Aware Compilation for Register File Energy Reduction

Alexander V. Veidenbaum, Marisa López-Vallejo, José Luis Ayala, 2004, International Journal of Parallel Programming.

Just in Time Load Balancing

Alexander V. Veidenbaum, Alexandru Nicolau, Rosario Cammarota, 2012, LCPC.

High performance annotation-aware JVM for Java cards

Alexander V. Veidenbaum, Alexandru Nicolau, Ana Azevedo, 2005, EMSOFT.

A Compiler-Assisted Cache Coherence Solution for Multiprcessors

Alexander V. Veidenbaum, A. Veidenbaum, 1986, ICPP.

A new pointer-based instruction queue design and its power-performance evaluation

Mateo Valero, Alexander V. Veidenbaum, Adrián Cristal, 2005, 2005 International Conference on Computer Design.

Polygonal Iteration Space Partitioning

Alexander V. Veidenbaum, Alexandru Nicolau, Mario Mango Furnari, 2016, LCPC.

Compiler-directed data prefetching in multiprocessors with memory hierarchies

Alexander V. Veidenbaum, Elana D. Granston, Edward H. Gornish, 1990, ICS '90.

Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors

Avesta Sasan, Houman Homayoun, Alexander V. Veidenbaum, 2008, LCTES '08.

A predictive decode filter cache for reducing power consumption in embedded processors

Weiyu Tang, Alexander V. Veidenbaum, Alexandru Nicolau, 2007, TODE.

Improving branch prediction accuracy in embedded processors in the presence of context switches

Alexander V. Veidenbaum, Sudeep Pasricha, S. Pasricha, 2003, Proceedings 21st International Conference on Computer Design.

Cache-aware iteration space partitioning

Alexander V. Veidenbaum, Alexandru Nicolau, Constantine D. Polychronopoulos, 2008, PPoPP.

Guest Editor's Introduction: Application-Specific Processors

Alexander V. Veidenbaum, 2004, IEEE Micro.

Proceedings of the 6th ACM conference on Computing frontiers

Alexander V. Veidenbaum, Georgi Gaydadjiev, Gearold R. Johnson, 2009 .

Architectural adaptation for power and performance

Rajesh Gupta, Weiyu Tang, Alexander V. Veidenbaum, 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

Combining flow and dependence analyses to expose redundant array accesses

Alexander V. Veidenbaum, Elana D. Granston, A. Veidenbaum, 1995, International Journal of Parallel Programming.

Retrospective: the Cedar system

David A. Padua, Alexander V. Veidenbaum, Constantine D. Polychronopoulos, 1998, ISCA '98.

Stride-directed prefetching for secondary caches

Alexander V. Veidenbaum, Sunil Kim, A. Veidenbaum, 1997, Proceedings of the 1997 International Conference on Parallel Processing (Cat. No.97TB100162).

Optimizing CAM-based instruction cache designs for low-power embedded systems

Alexander V. Veidenbaum, Juan L. Aragón, 2008, J. Syst. Archit..

Combining Prefetch Control and Cache Partitioning to Improve Multicore Performance

Alexander V. Veidenbaum, Junjie Shen, Gongjin Sun, 2019, 2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS).

Instructions-Wake-Up Mechanisms: Power and Timing Evaluation

Mateo Valero, Alexander V. Veidenbaum, Luis Villa, 2004 .

A hardware mechanism to reduce the energy consumption of the register file of in-order architectures

Alexander V. Veidenbaum, Marisa López-Vallejo, José Luis Ayala, 2008, Int. J. Embed. Syst..

Adaptive techniques for leakage power management in L2 cache peripheral circuits

Houman Homayoun, Alexander V. Veidenbaum, Jean-Luc Gaudiot, 2008, 2008 IEEE International Conference on Computer Design.

ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits

Avesta Sasan, Houman Homayoun, Alexander V. Veidenbaum, 2008, 2008 IEEE International Conference on Computer Design.

Detecting redundant accesses to array data

Alexander V. Veidenbaum, Elana D. Granston, 1991, Proceedings of the 1991 ACM/IEEE Conference on Supercomputing (Supercomputing '91).

Reducing leakage power in peripheral circuits of L2 caches

Houman Homayoun, Alexander V. Veidenbaum, 2007, 2007 25th International Conference on Computer Design.

An empirical study of the effect of source-level loop transformations on compiler stability

Zhi Chen, Josep Torrellas, David A. Padua, 2018, Proc. ACM Program. Lang..

MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits

Avesta Sasan, Houman Homayoun, Alexander V. Veidenbaum, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A partitioned instruction queue to reduce instruction wakeup energy

Mateo Valero, Alexander V. Veidenbaum, Adrián Cristal, 2004, Int. J. High Perform. Comput. Netw..

A content aware integer register file organization

Mateo Valero, Alexander V. Veidenbaum, Adrián Cristal, 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

Optimizing Program Performance via Similarity, Using a Feature-Agnostic Approach

Alexander V. Veidenbaum, Alexandru Nicolau, Rosario Cammarota, 2013, APPT.

Data-rate-aware FPGA-based acceleration framework for streaming applications

Alexander V. Veidenbaum, Alexandru Nicolau, Elaheh Bozorgzadeh, 2016, 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

Beyond memory cells for leakage and temperature control in sram-based units, the peripheral circuits story

Houman Homayoun, Alexander V. Veidenbaum, A. Veidenbaum, 2010 .

A simplified java bytecode compilation system for resource-constrained embedded processors

Alexander V. Veidenbaum, Alexandru Nicolau, Carmen Badea, 2007, CASES '07.

Chief: a parallel simulation environment for parallel systems

Alexander V. Veidenbaum, Hoichi Cheong, Pen-Chung Yew, 1991, [1991] Proceedings. The Fifth International Parallel Processing Symposium.

Efficient Scheduling of Nested Parallel Loops on Multi-Core Systems

Alexander V. Veidenbaum, Alexandru Nicolau, Constantine D. Polychronopoulos, 2009, 2009 International Conference on Parallel Processing.

Profile-based dynamic voltage scheduling using program checkpoints

Rajesh Gupta, Nikil D. Dutt, Alexander V. Veidenbaum, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Decoupled State-Execute Architecture

Mateo Valero, Alexander V. Veidenbaum, Adrián Cristal, 2005, ISHPC.

Towards an Achievable Performance for the Loop Nests

David A. Padua, Alexander V. Veidenbaum, Alexandru Nicolau, 2018, LCPC.

On the Determination of Inlining Vectors for Program Optimization

Alexander V. Veidenbaum, Alexandru Nicolau, Debora Donato, 2013, CC.

Probablistic Self-Scheduling

Milind Girkar, Xinmin Tian, Alexander V. Veidenbaum, 2006, Euro-Par.

Proceedings of the 14th international conference on Supercomputing

Alexander V. Veidenbaum, John Reynders, A. Veidenbaum, 2000 .

Tight analysis of the performance potential of thread speculation using spec CPU 2006

Milind Girkar, Xinmin Tian, Alexander V. Veidenbaum, 2007, PPOPP.

Management in Multiprocessors

Alexander V. Veidenbaum, Hoichi Cheong, 1990 .

Pruning hardware evaluation space via correlation-driven application similarity analysis

Alexander V. Veidenbaum, Alexandru Nicolau, Arun Kejariwal, 2011, CF '11.

On the performance potential of different types of speculative thread-level parallelism: The DL version of this paper includes corrections that were not made available in the printed proceedings

Milind Girkar, Xinmin Tian, Alexander V. Veidenbaum, 2006, ICS '06.

Instruction Cache Prefetching Using Multilevel Branch Prediction

Alexander V. Veidenbaum, A. Veidenbaum, 1997, ISHPC.

RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor

Nikil D. Dutt, Avesta Sasan, Houman Homayoun, 2010, HiPEAC.

Synchronization optimizations for efficient execution on multi-cores

Alexander V. Veidenbaum, Alexandru Nicolau, Guangqiang Li, 2009, ICS '09.

On the efficacy of call graph-level thread-level speculation

Milind Girkar, Xinmin Tian, Alexander V. Veidenbaum, 2010, WOSP/SIPEW '10.

University of Illinois project on language analysis for Lawrence Livermore National Laboratory. Final report

Alexander V. Veidenbaum, Pen-Chung Yew, D. A. Padua, 1981 .

A cache coherence scheme with fast selective invalidation

Alexander V. Veidenbaum, Hoichi Cheong, 1988, ISCA '88.

Using Hardware Counters to Predict Vectorization

Alexander V. Veidenbaum, Alexandru Nicolau, Zhi Chen, 2017, LCPC.

Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems

Houman Homayoun, Kazutoshi Wakabayashi, Alexander V. Veidenbaum, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

Adapting cache line size to application behavior

Rajesh K. Gupta, Weiyu Tang, Alexander V. Veidenbaum, 1999, ICS '99.

An effective write policy for software coherence schemes

Alexander V. Veidenbaum, Yung-Chin Chen, A. Veidenbaum, 1992, Proceedings Supercomputing '92.

Parallel machine architecture and compiler design facilities

David A. Padua, Alexander V. Veidenbaum, Pen-Chung Yew, 1990 .

Adaptive Line Size Cache

Rajesh Gupta, Weiyu Tang, Alexander V. Veidenbaum, 1999 .

On Interaction between Interconnection Network Design and Latency Hiding Techniques in Multiprocessors

Alexander V. Veidenbaum, Sunil Kim, A. Veidenbaum, 2000, The Journal of Supercomputing.

An Integrated Hardware/Software Solution for Effective Management of Local Storage in High-Performance Systems

Alexander V. Veidenbaum, Elana D. Granston, A. Veidenbaum, 1991, ICPP.

Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium® architecture

Alexander V. Veidenbaum, Alexandru Nicolau, Arun Kejariwal, 2007, SIGMETRICS '07.

Acceleration Framework for FPGA Implementation of OpenVX Graph Pipelines

Alexander V. Veidenbaum, Alexandru Nicolau, Payman Behnam, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Reducing power consumption for high-associativity data caches in embedded processors

Alexander V. Veidenbaum, Alexandru Nicolau, Dan Nicolaescu, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Effective Evaluation of Multi-core Based Systems

Alexander V. Veidenbaum, Alexandru Nicolau, Rosario Cammarota, 2013, 2013 IEEE 12th International Symposium on Parallel and Distributed Computing.

CAMFAS: A Compiler Approach to Mitigate Fault Attacks via Enhanced SIMDization

Zhi Chen, Nahid Farhady Ghalaty, Alexander V. Veidenbaum, 2017, 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC).

Compiler-directed cache management in multiprocessors

Alexander V. Veidenbaum, Hoichi Cheong, A. Veidenbaum, 1990, Computer.

An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors1

Alexander V. Veidenbaum, Edward H. Gornish, A. Veidenbaum, 1994, 1994 Internatonal Conference on Parallel Processing Vol. 2.

Efficient simulation of large-scale Spiking Neural Networks using CUDA graphics processors

Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau, 2009, 2009 International Joint Conference on Neural Networks.

Innovative Architecture for Future Generation High-Performance Processors and Systems

Alexander V. Veidenbaum, Kazuki Joe, K. Joe, 2003, Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003.

EdgeAvatar: An Edge Computing System for Building Virtual Beings

Alexander V. Veidenbaum, Alexandru Nicolau, Tony Givargis, 2021, Electronics.

Reducing Register File Energy Consumption using Compiler Support

Alexander V. Veidenbaum, José L. Ayala, 2002 .

AFFIX: Automatic Acceleration Framework for FPGA Implementation of OpenVX Vision Algorithms

Alexander V. Veidenbaum, Alexandru Nicolau, Elaheh Bozorgzadeh, 2019, FPGA.