V. Kamakoti

发表

V. Kamakoti, V. Kamakoti, 2016 .

Efficient Randomized Incremental Algorithm For The Closest Pair Problem Using Leafary Trees

C. Pandu Rangan, V. Kamakoti, Kamala Krithivasan, 1995, COCOON.

A Framework for Automatic Assembly Program Generator (A^2PG) for Verification and Testing of Processor Cores

V. Kamakoti, Kailasnath Maneparambil, K. Uday Bhaskar, 2005, 14th Asian Test Symposium (ATS'05).

The Colored Sector Search Tree: A Dynamic Data Structure for Efficient High Dimensional Nearest-Foreign-Neighbor Queries

C. Pandu Rangan, V. Kamakoti, Thomas Graf, 1998, COCOON.

Pseudo-online testing methodologies for various components of field programmable gate arrays

V. Kamakoti, L. Kalyan Kumar, Aditya S. Ramani, 2005, Microprocess. Microsystems.

Motion Vector Recovery Based Error Concealment for H.264 Video Communication: A Review

V. Kamakoti, Kavish Seth, Sumana Srinivasan, 2011 .

SHAKTI-F: A Fault Tolerant Microprocessor Architecture

V. Kamakoti, Sukrat Gupta, Neel Gala, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

A universal random test generator for functional verification of microprocessors and system-on-chip

V. Kamakoti, K. Uday Bhaskar, M. Prasanth, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Adaptive finite element analysis on a parallel and distributed environment

V. Kamakoti, C. S. Krishnamoorthy, V. Annamalai, 1999, Parallel Comput..

Post-Synthesis Circuit Techniques for Runtime Leakage Reduction

V. Kamakoti, Nitin Chandrachoodan, Seetal Potluri, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Variation-Tolerant, Power-Safe Pattern Generation

V. Kamakoti, C. P. Ravikumar, V. R. Devanathan, 2007, IEEE Design & Test of Computers.

A function generator-based reconfigurable system

V. Kamakoti, V. Garg, V. Chandrasekhar, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Dynamic coding technique for low-power data bus

V. Kamakoti, M. Madhu, V. Srinivasa Murty, 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

Tunable stochastic computing using layered synthesis and temperature adaptive voltage scaling

V. Kamakoti, V. R. Devanathan, Neel Gala, 2013, Fifth Asia Symposium on Quality Electronic Design (ASQED 2013).

Memmap: technology mapping algorithm for area reduction in FPGAs with embedded memory arrays using reconvergence analysis

V. Kamakoti, Jayaram Bobba, A. Manoj Kumar, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

On-Line Location of Multiple Faults in LUT Based Reconfigurable Systems

V. Kamakoti, L. Kalyan Kumar, Aditya S. Ramani, 2003, VLSI.

Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation

V. Kamakoti, S. Srinivasan, Kavish Seth, 2010, IEEE Transactions on Broadcasting.

Sparse Dominance Queries for Many Points in Optimal Time and Space

V. Kamakoti, Thomas Graf, 1997, Inf. Process. Lett..

A genetic approach to gateless custom VLSI design flow

V. Kamakoti, Noor Mahammad Sk, M. Shoaib, 2007, 2007 Internatonal Conference on Microelectronics.

Detecting SEU-caused routing errors in SRAM-based FPGAs

V. Kamakoti, Narayanan Vijaykrishnan, Vikram Chandrasekhar, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Parallel Partitioning Techniques for Logic Minimization Using Redundancy Identification

V. Kamakoti, B. Jayaram, A. Manoj Kumar, 2003, HiPC.

An Evolutionary Algorithm for Automatic Spatial Partitioning in Reconfigurable Environments

V. Kamakoti, Sivaprakasam Suresh, Permandla Pratibha, 2004, MICAI.

Interconnect Aware Test Power Reduction

V. Kamakoti, Nitin Chandrachoodan, Seetal Potluri, 2012, J. Low Power Electron..

Controllability-driven Power Virus Generation for Digital Circuits

V. Kamakoti, Vivekananda M. Vedula, Karthik Gururaj, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

DP-fill: A dynamic programming approach to X-filling for minimizing peak test power in scan tests

V. Kamakoti, Shiv Govind Singh, Seetal Potluri, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms

V. Kamakoti, C. P. Ravikumar, V. R. Devanathan, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs

V. Kamakoti, Narayanan Vijaykrishnan, Vikram Chandrasekhar, 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses

V. Kamakoti, Vishal Gupta, Madhu Mutyam, 2006, J. Low Power Electron..

A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips

V. Kamakoti, Nitin Chandrachoodan, Seetal Potluri, 2017, 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Efficient algorithms for prefix and general prefix computations on distributed shared memory systems with applications

V. Kamakoti, N. Balakrishnan, 1997, Proceedings 1997 International Conference on Parallel and Distributed Systems.

An Architecture for Real Time Face Recognition Using WMPCA

V. Kamakoti, Sukhendu Das, A. Pavan Kumar, 2004, ICVGIP.

MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks

V. Kamakoti, R. Manimegalai, B. Jayaram, 2004, FPL.

Complete Decoupling From Caches and Achieving Highly Concurrent Transactions, ACM SIGOPS Operating Systems Review

V. Kamakoti, K. Kunal, K. George, 2009 .

A novel method for online in-place detection and location of multiple interconnect faults in SRAM based FPGAs

V. Kamakoti, L. Kalyan Kumar, Aditya S. Ramani, 2003, 2003 Test Symposium.

Power Virus Generation Using Behavioral Models of Circuits

V. Kamakoti, Vivekananda M. Vedula, K. Najeeb, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

PERI: A Posit Enabled RISC-V Core pdf

V. Kamakoti, Chester Rebeiro, Neel Gala, 2019, ArXiv.

A principal component neural network-based face recognition system and ASIC implementation

V. Kamakoti, N. Sudha, Chakka Siva Sai Prasanna, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

A function generator-based reconfigurable system

V. Kamakoti, Vikram Chandrasekhar, Vivek Garg, 2005, ASP-DAC.

On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores

V. Kamakoti, C. P. Ravikumar, V. R. Devanathan, 2006, J. Low Power Electron..

Testable Clock Routing Architecture for Field Programmable Gate Arrays

V. Kamakoti, L. Kalyan Kumar, Aditya S. Ramani, 2003, FPL.

HTM design spaces: complete decoupling from caches and achieving highly concurrent transactions

V. Kamakoti, Kunal Korgaonkar, K. George, 2009, OPSR.

ReMap: A Novel Automated Peephole Optimization Based Approach for Logic, Delay and Power Minimization

V. Kamakoti, K. Shyamala, 2014, J. Low Power Electron..

Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test

V. Kamakoti, C.P. Ravikumar, V.R. Devanathan, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

An Optimal Algorithm for Reconstructing a Binary Tree

C. Pandu Rangan, V. Kamakoti, 1992, Inf. Process. Lett..

A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs

V. Kamakoti, Vikram Chandrasekhar, Vivek Garg, 2005, ASP-DAC.

MemMap-pd: performance driven technology mapping algorithm for FPGAs with embedded memory arrays

V. Kamakoti, R. Manimegalai, B. Jayaram, 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

Novel SAT-Based Peak Dynamic Power Estimation for Digital Circuits

V. Kamakoti, K. Shyamala, J. Vimalkumar, 2009, J. Low Power Electron..

A parallel genetic approach to the placement problem for field programmable gate arrays

V. Kamakoti, Sivaprakasam Suresh, Siva Nageswara Rao Borra, 2003, Proceedings International Parallel and Distributed Processing Symposium.

A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs

V. Kamakoti, V. Garg, V. Chandrasekhar, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Efficient Parallel Algorithms for Permutation Graphs

C. Pandu Rangan, V. Kamakoti, K. Arvind, 1995, J. Parallel Distributed Comput..

Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs

V. Kamakoti, E.S.S. Reddy, V.C.M. Sashikanth, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

An area and configuration-bit optimized CLB architecture and timing-driven packing for FPGAs

V. Kamakoti, Vikram Chandrasekhar, Vivek Garg, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

ROSY: recovering processor and memory systems from hard errors

V. Kamakoti, Karthik Raghavan, 2012, OPSR.

An Efficient Heuristic for Peak Capture Power Minimization During Scan-Based Test

V. Kamakoti, Seetal Potluri, Ch. Sobhan Babu, 2013, J. Low Power Electron..

A novel three phase parallel genetic approach to routing for field programmable gate arrays

V. Kamakoti, Sivaprakasam Suresh, Annamalai Muthukaruppan, 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

A Hardware-Directed Face Recognition System Based on Local Eigen-analysis with PCNN

V. Kamakoti, N. Sudha, Chakka Siva Sai Prasanna, 2004, ICONIP.

SHAKTI Processors: An Open-Source Hardware Initiative

V. Kamakoti, Rahul Bodduna, Neel Gala, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

A Simulation Based Buffer Sizing Algorithm for Network on Chips

Luca Benini, V. Kamakoti, Srinivasan Murali, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Placement and routing for 3D-FPGAs using reinforcement learning and support vector machines

V. Kamakoti, R. Manimegalai, Balaraman Ravindran, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Framework for Selective Flip-Flop Replacement for Soft Error Mitigation

V. Kamakoti, V. R. Devanathan, Pavan Vithal Torvi, 2015, 2015 28th International Conference on VLSI Design.

Building Root of Trust

V. Kamakoti, Sanjay Burman, 2012, FPT 2012.

Prime Numbers are High Coverage Test Vectors

V. Kamakoti, Akanksha Jain, Vasanth Ramesh, 2009 .

Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions

V. Kamakoti, Milan Patnaik, V. R. Devanathan, 2013, J. Low Power Electron..

On Power-profiling and Pattern Generation for Power-safe Scan Tests

V. Kamakoti, C. P. Ravikumar, V. R. Devanathan, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits

V. Kamakoti, Vivekananda M. Vedula, Karthik Gururaj, 2007, J. Low Power Electron..

SER mitigation technique through selective flip-flop replacement

V. Kamakoti, V. R. Devanathan, Pavan Vithal Torvi, 2015, 2015 6th Asia Symposium on Quality Electronic Design (ASQED).

An Efficient Randomized Algorithm for the Closest Pair Problem on Colored Point Sets

C. Pandu Rangan, V. Kamakoti, Kamala Krithivasan, 1995, Nord. J. Comput..

A special purpose silicon compiler for designing supercomputing VLSI systems

V. Kamakoti, N. Venkateswaran, S. Rangarajan, 1991 .

NOC: Introduction to Information Security I

V. Kamakoti, 2015 .

Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimization

V. Kamakoti, L. Srivani, Shankar Ganesh, 2015, Appl. Soft Comput..

System-on-programmable-chip implementation for on-line face recognition

V. Kamakoti, Sukhendu Das, A. Pavan Kumar, 2007, Pattern Recognit. Lett..

Thread Synchronization: From Mutual Exclusion to Transactional Memory

V. Kamakoti, Kunal Korgaonkar, Kunal Korgaonkar, 2011 .

Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications

V. Kamakoti, V. R. Devanathan, V. Visvanathan, 2015, J. Low Power Electron..

Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures

V. Kamakoti, George Kurian, Srivaths Ravi, 2009, J. Low Power Electron..

Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only)

V. Kamakoti, Narayanan Vijaykrishnan, Vikram Chandrasekhar, 2005, FPGA '05.

FPGA based agile algorithm-on-demand coprocessor

V. Kamakoti, Sanjay Burman, S. Vinay, 2005, Design, Automation and Test in Europe.

Face Recognition Using Weighted Modular Principle Component Analysis

V. Kamakoti, Sukhendu Das, A. Pavan Kumar, 2004, ICONIP.

SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis

V. Kamakoti, R. Manimegalai, B. Jayaram, 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

A Novel Algorithm for Fast Synthesis of DNA Probes on Microarrays

V. Kamakoti, A. Bhattacharya, Shri K. V. Srinivasan, 2013, JETC.

Approximate Error Detection With Stochastic Checkers

V. Kamakoti, Anand Raghunathan, Swagath Venkataramani, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

XStat: Statistical X-Filling Algorithm for Peak Capture Power Reduction in Scan Tests

V. Kamakoti, Shankar Balachandran, Seetal Potluri, 2014, J. Low Power Electron..

ChADD: An ADD Based Chisel Compiler with Reduced Syntactic Variance

V. Kamakoti, Vikas Chauhan, Neel Gala, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

An artificial neural network guided parallel genetic approach to the routing problem for field programmable gate arrays

V. Kamakoti, S. Suresh, A. Muthukaruppan, 2002, Proceedings of the 9th International Conference on Neural Information Processing, 2002. ICONIP '02..

PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information

V. Kamakoti, Nitin Chandrachoodan, Seetal Potluri, 2013, 2013 18th IEEE European Test Symposium (ETS).

Studies onthePerformance ofTwoNewBusArbitration Schemes forMulti- CoreProcessors

V. Kamakoti, N. Ramasubramanian, P. Krishnan, 2009 .

Efficient Grouping of Fail Chips for Volume Yield Diagnostics

V. Kamakoti, Ananta K. Majhi, Lavanya Jagan, 2009, 2009 22nd International Conference on VLSI Design.

An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators

V. Kamakoti, Narayanan Vijaykrishnan, Xueqing Li, 2017, ACM J. Emerg. Technol. Comput. Syst..

Automatic Constraint Based Test Generation for Behavioral HDL Models

V. Kamakoti, Vivekananda M. Vedula, Vishnu Vardhan Reddy Konda, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test

V. Kamakoti, C. P. Ravikumar, V. R. Devanathan, 2007, 2007 IEEE International Test Conference.

Fast motion vector recovery algorithm in H.264 video streams

V. Kamakoti, Kavish Seth, Sumana Srinivasan, 2010, Electronic Imaging.

Efficient Randomized Parallel Algorithm for the Closest Pair Problem in D-dimension

C. Pandu Rangan, V. Kamakoti, P. Jagan Mohan, 1994, IFIP Congress.

A novel approach to the placement and routing problems for field programmable gate arrays

V. Kamakoti, Sivaprakasam Suresh, Siva Nageswara Rao Borra, 2007, Appl. Soft Comput..

ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs

V. Kamakoti, V. R. Devanathan, V. Visvanathan, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

Impact of Temperature on Test Quality

V. Kamakoti, Camelia Hora, Bram Kruseman, 2010, 2010 23rd International Conference on VLSI Design.

Efficient motion vector recovery algorithm for H.264 using directional interpolation

V. Kamakoti, Kavish Seth, Sumana Srinivasan, 2010 .

An efficient algorithm for the nearest smallers problem on distributed shared memory systems with applications

V. Kamakoti, T. Graf, N. Balakrishnan, 1997, Proceedings High Performance Computing on the Information Superhighway. HPC Asia '97.

A parallel architectural implementation of the New Three-Step Search algorithm for block motion estimation

V. Kamakoti, P. Rangarajan, S. Srinivasan, 2004, 17th International Conference on VLSI Design. Proceedings..

ProMAC: A proactive model predictive control based MAC protocol for cognitive radio vehicular networks

V. Kamakoti, Milan Patnaik, N. Sathya Narayanan, 2016, Comput. Commun..

An Efficient Digital Architecture for Principal Component Neural Network and its FPGA Implementation

V. Kamakoti, N. Sudha, C. H. Siva Sai Prasanna, 2007 .

Delay and peak power minimization for on-chip buses using temporal redundancy

V. Kamakoti, Vishal Gupta, Madhu Mutyam, 2006, GLSVLSI '06.

A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction

V. Kamakoti, C. P. Ravikumar, V. R. Devanathan, 2008, J. Low Power Electron..

Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs

V. Kamakoti, V. R. Devanathan, V. Visvanathan, 2012, J. Low Power Electron..

A bus encoding technique for power and cross-talk minimization

V. Kamakoti, R. Manimegalai, Madhu Mutyam, 2004, 17th International Conference on VLSI Design. Proceedings..

A Review of Algorithms for Border Length Minimization Problem

V. Kamakoti, Sumana Srinivasan, A. Bhattacharya, 2014 .

PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test

V. Kamakoti, C. P. Ravikumar, V. R. Devanathan, 2007, 2007 IEEE International Test Conference.

Towards Quick Solutions for Generalized Placement Problem

V. Kamakoti, S. Srinivasan, A. Bhattacharya, 2011, 2011 International Symposium on Electronic System Design.

Studies on the Performance of Two New Bus Arbitration Schemes for MultiCore Processors

V. Kamakoti, P. Krishnan, N. Ramasubramanian, 2009, 2009 IEEE International Advance Computing Conference.

PROLEMus: A Proactive Learning-Based MAC Protocol Against PUEA and SSDF Attacks in Energy Constrained Cognitive Radio Networks

V. Kamakoti, Milan Patnaik, Vashek Matyáš, 2019, IEEE Transactions on Cognitive Communications and Networking.

A Parallel Evolutionary Approach to Spatial Partitioning in Reconfigurable Environments

V. Kamakoti, Sivaprakasam Suresh, Permandla Pratibha, 2003, IICAI.

Hardware based genetic evolution of self-adaptive arbitrary response FIR filters

V. Kamakoti, Sk. Noor Mahammad, Shoaib Mohammed, 2011, Appl. Soft Comput..

Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs

V. Kamakoti, Narayanan Vijaykrishnan, Vikram Chandrasekhar, 2005, ASP-DAC.

CAD for VLSI Design II

V. Kamakoti, S. Balachandran, 2000 .

DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing

V. Kamakoti, Nitin Chandrachoodan, Seetal Potluri, 2015, ACM Trans. Design Autom. Electr. Syst..

An optimal parallel algorithm for the all-nearest-foreign-neighbors problem in arbitrary dimensions

C. Pandu Rangan, V. Kamakoti, Thomas Graf, 1997, Proceedings Fourth International Conference on High-Performance Computing.

MLTimer: Leakage Power Minimization in Digital Circuits Using Machine Learning and Adaptive Lazy Timing Analysis

V. Kamakoti, Milan Patnaik, Seetal Potluri, 2018, J. Low Power Electron..

Synthetic Benchmark Digital Circuits: A Survey

V. Kamakoti, L. Srivani, 2012 .

Karna: A Gate-Sizing based Security Aware EDA Flow for Improved Power Side-Channel Attack Protection

V. Kamakoti, Chester Rebeiro, Prasanna Karthik Vairam, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands

Luca Benini, V. Kamakoti, Srinivasan Murali, 2012, J. Electr. Comput. Eng..

Online detection and diagnosis of multiple configuration upsets in LUTs of SRAM-based FPGAs

V. Kamakoti, Narayanan Vijaykrishnan, Vikram Chandrasekhar, 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

Ultra folded high-speed architectures for Reed Solomon decoders

V. Kamakoti, S. Srinivasan, Kavish Seth, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection

V. Kamakoti, Anand Raghunathan, Swagath Venkataramani, 2016, ISLPED.

SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis

V. Kamakoti, B. Jayaram, A. Manoj Kumar, 2004, FPGA '04.

PERI

V. Kamakoti, Chester Rebeiro, Neel Gala, 2021, ACM Trans. Archit. Code Optim..

Efficient Building Blocks for Reversible Sequential Circuit Design

V. Kamakoti, Sk. Noor Mahammad, Siva Kumar Sastry Hari, 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

H-Pattern: A Hybrid Pattern Based Dynamic Branch Predictor with Performance Based Adaptation

V. Kamakoti, Milan Patnaik, Samir Otiv, 2014 .