S. Khatri

发表

Optimum Reverse Body Biasing for Leakage Minimization

N. Jayakumar, S. Paul, R. Garg, 2010 .

Multi-Valued Network Compaction using Redundancy Removal

R. Brayton, A. Sangiovanni-Vincentelli, S. Khatri, 2017 .

Application of Max-SAT-based ATPG to optimal cancer therapy design

S. Khatri, P. Lin, 2012, BMC Genomics.

Multi-Valued Network Simplification using Redundancy Removal

S. Khatri, 1998 .

VIS: A System for Verification and Synthesis

Tiziano Villa, Stephen A. Edwards, Szu-Tsung Cheng, 1996, CAV.

Exploring a circuit design approach based on one-hot multi-valued domino logic

Dibakar Gope, S. Khatri, P. Lin, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

8 B . 3 A GENERIC RADAR PROCESSOR DESIGN USINGSOFTWARE DEFINED RADIO

S. Khatri, Tom Brimeyer, C. Martin, 2007 .

A Multi-layer Area Routing Methodology using a Boolean Satisfiability based Router

A. Sangiovanni-Vincentelli, S. Khatri, 2017 .

TIMING AWARE PARTITIONING FOR MULTI-FPGA BASED LOGIC SIMULATION USING TOP-DOWN SELECTIVE FLATTENING

S. Khatri, 2012 .

Minimum leakage vector computation using weighted partial MaxSAT

K. Gulati, S. Khatri, Amrinder Singh, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

VIS

R. Brayton, A. Sangiovanni-Vincentelli, G. Hachtel, 2021 .

Logic Synthesis for Genetic Diseases: Modeling Disease Behavior Using Boolean Networks

S. Khatri, P. Lin, 2013 .

A novel VLSI layout fabric for deep sub-micron applications

R. Brayton, A. Sangiovanni-Vincentelli, A. Mehrotra, 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

A metal and via maskset programmable VLSI design methodology using PLAs

Sunil P. Khatri, Nikhil Jayakumar, N. Jayakumar, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

SPFD-based Wire Removal in a Network of PLAs

R. Brayton, A. Sangiovanni-Vincentelli, A. Kuehlmann, 1999 .

Don't Caxe Wires in Logical/Physical Design

R. Brayton, S. Khatri, Yunjian Jiang, 2017 .

Towards More Power Efficient Ip Lookup Engines towards More Power Efficient Ip Lookup Engines

D. Walker, S. Khatri, R. Mahapatra, 2005 .

An efficient and regular routing methodology for datapath designsusing net regularity extraction

Sunil P. Khatri, Sabyasachi Das, S. Khatri, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A metal and via maskset programmable VLSI design methodology using PLAs

N. Jayakumar, S. Khatri, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells

S. Vrudhula, S. Khatri, G. Singh, 2022, IEEE Transactions on Circuits and Systems I: Regular Papers.

Construction of ROBDDs

R. Brayton, A. Narayan, J. Jain, 2016 .

Critical remarks on Landauer's principle of erasure-dissipation: Including notes on Maxwell demons and Szilard engines

L. Kish, C. Granqvist, S. Khatri, 2014, 2015 International Conference on Noise and Fluctuations (ICNF).

A DELAY-EFFICIENT RADIATION-HARD DIGITAL DESIGN APPROACH USING CODE WORD STATE PRESERVING (CWSP) ELEMENTS A Thesis by CHARU NAGPAL

S. Khatri, 2022 .

A Robust Window-Based Multi-node Minimization Technique Using Boolean Relations

Jeff L. Cobb, S. Khatri, Kanupriya Gulati, 2011 .

Compositional Techniques for Mixed Bottom-Up/Top-Down

R. Brayton, A. Sangiovanni-Vincentelli, M. Fujita, 1999 .

Analytical Determination of Radiation-induced Pulse Width in Combinational Circuits

R. Garg, S. Khatri, 2010 .

CIDAN-XE: Computing in DRAM with Artificial Neurons

S. Vrudhula, S. Khatri, G. Singh, 2022, Frontiers in Electronics.

CIDAN: Computing in DRAM with Artificial Neurons

Sarma Vrudhula, Sunil Khatri, Ankit Wagle, 2021, 2021 IEEE 39th International Conference on Computer Design (ICCD).

A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells

Sarma Vrudhula, Sunil Khatri, Ankit Wagle, 2020, 2020 IEEE 38th International Conference on Computer Design (ICCD).

A Statistical Methodology for Post-Fabrication Weight Tuning in a Binary Perceptron

Sarma Vrudhula, Elham Azari, Sunil Khatri, 2020, 2020 21st International Symposium on Quality Electronic Design (ISQED).

Threshold Logic in a Flash

S. Vrudhula, S. Khatri, G. Singh, 2019, 2019 IEEE 37th International Conference on Computer Design (ICCD).

Determining Gene Function in Boolean Networks using SAT

Sunil P. Khatri, Pey-Chang Kent Lin, S. Khatri, 2014 .

ATPG for Cancer Therapy

Sunil P. Khatri, Pey-Chang Kent Lin, S. Khatri, 2014 .

Determining gene function in boolean networks using boolean satisfiability

Sunil P. Khatri, Pey-Chang Kent Lin, S. Khatri, 2012, Proceedings 2012 IEEE International Workshop on Genomic Signal Processing and Statistics (GENSIPS).

Application of logic synthesis to the understanding and cure of genetic diseases

Sunil P. Khatri, Pey-Chang Kent Lin, S. Khatri, 2012, DAC Design Automation Conference 2012.

Efficient cancer therapy using Boolean networks and Max-SAT-based ATPG

Sunil P. Khatri, Pey-Chang Kent Lin, S. Khatri, 2011, 2011 IEEE International Workshop on Genomic Signal Processing and Statistics (GENSIPS).

Computation using noise-based logic: efficient string verification over a slow communication channel

Laszlo B. Kish, Tamás Horváth, Sunil P. Khatri, 2010, ArXiv.

Fast and Highly Scalable Bayesian MDP on a GPU Platform

Jiang Hu, Frank Liu, He Zhou, 2017, BCB.

A GPU-based implementation of a sensor tasking methodology

Sunil P. Khatri, Monther Abusultan, Suman Chakravorty, 2016, 2016 19th International Conference on Information Fusion (FUSION).

An area-efficient Ternary CAM design using floating gate transistors

Sunil P. Khatri, Viacheslav V. Fedorov, Monther Abusultan, 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

An Engineering Change Methodology Using Simulation Relations.

Robert K. Brayton, Alberto Sangiovanni-Vincentelli, Amit Narayan, 1999 .

Decomposition Techniques for Efficient ROBDD Construction

Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Masahiro Fujita, 1996, FMCAD.

A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements

Sunil P. Khatri, Rajesh Garg, Charu Nagpal, 2008, 2008 Design, Automation and Test in Europe.

Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction

Weiping Shi, Sunil P. Khatri, Kanupriya Gulati, 2008, IET Comput. Digit. Tech..

A Survey of Software and Hardware Approaches to Performing Read Alignment in Next Generation Sequencing

Aniruddha Datta, Ahmad Al Kawam, Sunil Khatri, 2017, IEEE/ACM Transactions on Computational Biology and Bioinformatics.

Instantaneous noise-based logic pdf

Ferdinand Peper, Laszlo B. Kish, Sunil P. Khatri, 2010, ArXiv.

Noise-based logic hyperspace with the superposition of 2N states in a single wire

Laszlo B. Kish, Sunil Khatri, Swaminathan Sethuraman, 2009, 0901.3947.

Efficient arithmetic sum-of-product (SOP) based Multiple Constant Multiplication (MCM) for FFT

Sunil P. Khatri, Vinay Karkala, Joseph Wanstrath, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems

Olgica Milenkovic, Sunil P. Khatri, Vijay Nagarajan, 2004, IEEE Global Telecommunications Conference, 2004. GLOBECOM '04..

A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications

Edgar Sánchez-Sinencio, Sunil P. Khatri, Didem Zeliha Turker, 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

GPU acceleration for Bayesian control of Markovian genetic regulatory networks

Jiang Hu, Frank Liu, Mohammadmahdi R. Yousefi, 2016, 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics (BHI).

Addressing the timing closure problem by integrating logic optimization and placement

Alberto L. Sangiovanni-Vincentelli, Wilsin Gosti, Sunil P. Khatri, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

A Plain-Text Incremental Compression (PIC) Technique with Fast Lookup Ability

Abbas Fairouz, Sunil P. Khatri, Kunal Bharathi, 2018, 2018 IEEE 36th International Conference on Computer Design (ICCD).

A Variation Tolerant Circuit Design Approach using Parallel Gates

S. Khatri, Rajesh Garg, 2009 .

TD3lite: FPGA Acceleration of Reinforcement Learning with Structural and Representation Optimizations

S. Khatri, Jiangkun Hu, Chan-Wei Hu, 2022, International Conference on Field-Programmable Logic and Applications.

Demons: Maxwell's demon, Szilard's engine and Landauer's erasure-dissipation

Laszlo B. Kish, Sunil P. Khatri, He Wen, 2014 .

Information, Noise, and Energy Dissipation: : Laws, Limits, and Applications

Laszlo B. Kish, Sunil P. Khatri, Ferdinand Peper, 2017 .

Response to “Comment on ‘Zero and negative energy dissipation at information-theoretic erasure”’

Ferdinand Peper, Laszlo B. Kish, Claes-Goran Granqvist, 2015, ArXiv.

Zero and negative energy dissipation at information-theoretic erasure

Laszlo B. Kish, Claes-Göran Granqvist, Sunil P. Khatri, 2015, ArXiv.

Broadband impedance matching for inductive interconnect in VLSI packages

Brock J. LaMeres, Sunil P. Khatri, S. Khatri, 2005, 2005 International Conference on Computer Design.

Fast, Ring-Based Design of 3-D Stacked DRAM

Sunil P. Khatri, Andrew J. Douglass, S. Khatri, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fast, Ring-Based Design of 3D Stacked DRAM

Sunil P. Khatri, Andrew J. Douglass, S. Khatri, 2017, 2017 IEEE International Conference on Computer Design (ICCD).

A GPU-CPU heterogeneous algorithm for NGS read alignment

Aniruddha Datta, Sunil P. Khatri, Ahmad Al Kawam, 2018, Int. J. Comput. Biol. Drug Des..

Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flattening

Sunil P. Khatri, Pey-Chang Kent Lin, Subramanian Poothamkurissi Swaminathan, 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit

S. Khatri, Rajesh Garg, 2009, 2009 IEEE International Conference on Computer Design.

Exploring topologies for source-synchronous ring-based Network-on-Chip

Sunil P. Khatri, Rabi N. Mahapatra, Ayan Mandal, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Fast circuit simulation on graphics processing units

Sunil P. Khatri, Kanupriya Gulati, John F. Croix, 2009, 2009 Asia and South Pacific Design Automation Conference.

Multi-valued logic synthesis

Robert K. Brayton, Sunil P. Khatri, R. Brayton, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications

Sunil P. Khatri, Pey-Chang Kent Lin, S. Khatri, 2010, GLSVLSI '10.

A Homomorphic Encryption Scheme Based on Affine Transforms

He Zhou, Sunil P. Khatri, Kyle Loyka, 2018, ACM Great Lakes Symposium on VLSI.

FPGA-based hardware acceleration for Boolean satisfiability

Srinivas Patil, Sunil P. Khatri, Abhijit Jas, 2009, TODE.

Accelerating Boolean Satisfiability on a Custom IC

Sunil P. Khatri, Kanupriya Gulati, S. Khatri, 2010 .

Noise-Based Logic and Computing: From Boolean Logic Gates to Brain Circuitry and Its Possible Hardware Realization

Laszlo B. Kish, Sergey M. Bezrukov, Sunil P. Khatri, 2009, IWNC.

Noise-based Deterministic Logic and Computing: a Brief Survey

Ferdinand Peper, Laszlo B. Kish, Sergey M. Bezrukov, 2010, Int. J. Unconv. Comput..

Towards acceleration of fault simulation using Graphics Processing Units

Sunil P. Khatri, Kanupriya Gulati, S. Khatri, 2008, 2008 45th ACM/IEEE Design Automation Conference.

A fast, source-synchronous ring-based network-on-chip design

Sunil P. Khatri, Rabi N. Mahapatra, Ayan Mandal, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Fast Network-on-Chip Design

Sunil P. Khatri, Rabi N. Mahapatra, Ayan Mandal, 2014 .

Engineering change in a non-deterministic FSM setting

Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Amit Narayan, 1996, 33rd Design Automation Conference Proceedings, 1996.

SAT-based ATPG using multilevel compatible don't-cares

Sunil P. Khatri, Nikhil Saluja, Kanupriya Gulati, 2008, TODE.

Generalized buffering of PTL logic stages using Boolean division

Sunil P. Khatri, Rajesh Garg, S. Khatri, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Efficient SAT-based combinational ATPG using multi-level don't-cares

Sunil P. Khatri, Nikhil Saluja, S. Khatri, 2005, IEEE International Conference on Test, 2005..

Cross-talk noise immune VLSI design using regular layout fabrics

Robert K. Brayton, Alberto Sangiovanni-Vincentelli, Sunil P. Khatri, 2001 .

Improving FPGA routability using network coding

Sunil P. Khatri, Kanupriya Gulati, S. Khatri, 2008, GLSVLSI '08.

A novel hardware hash unit design for modern microprocessors

Abbas Fairouz, Sunil P. Khatri, Monther Abusultan, 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

Zero and negative energy dissipation at information-theoretic erasure

L. Kish, C. Granqvist, F. Peper, 2015, Journal of Computational Electronics.

A Novel Pseudo-Flash Based Digital Low Dropout (LDO) Voltage Regulator

S. Vrudhula, S. Khatri, Cheng-Yen Lee, 2023, 2023 24th International Symposium on Quality Electronic Design (ISQED).

Inference of gene predictor set using Boolean satisfiability

Sunil P. Khatri, Pey-Chang Kent Lin, S. Khatri, 2010, 2010 IEEE International Workshop on Genomic Signal Processing and Statistics (GENSIPS).

Predictor Set Inference using SAT

Sunil P. Khatri, Pey-Chang Kent Lin, S. Khatri, 2014 .