T. Mak

发表

Dynamic On-Chip Thermal Optimization for 3 D Networks-on-Chip

F. Xia, A. Yakovlev, R. Al-Dujaily, 2012 .

Proceedings of the Nineteenth UK Asynchronous Forum

S. Furber, Y. Cheung, D. Sokolov, 2007 .

Wired layer : BER ∝ 10-14 Wireless node Wired node Wireless channel : BER ∝ 10-7 Wired link dCT

Michael Opoku Agyeman, A. Yakovlev, K. Tong, 2016 .

Restoration of Cerebellum Passage-of-Time Functionality Using a Scalable FPGA-based Granular Layer

P. Degenaar, T. Mak, C. Tin, 2014 .

FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation

Terrence S. T. Mak, Kai-Pui Lam, K. Lam, 2004, FPL.

Embedded computation of maximum-likelihood phylogeny inference using platform FPGA

Terrence S. T. Mak, Kai-Pui Lam, K. Lam, 2004, Proceedings. 2004 IEEE Computational Systems Bioinformatics Conference, 2004. CSB 2004..

Large-Scale On-Chip Dynamic Programming Network Inferences Using Moderated Inter-core Communication

Terrence S. T. Mak, Alexandre Yakovlev, Steve B. Furber, 2012, 2012 12th International Conference on Application of Concurrency to System Design.

A scalable FPGA-based design for field programmable large-scale ion channel simulations

Chi-Sang Poon, Terrence S. T. Mak, Alexandre Yakovlev, 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

Network-on-Chip Multicast Architectures Using Hybrid Wire and Surface-Wave Interconnects

Terrence Mak, Nizar Dahir, Alex Yakovlev, 2018, IEEE Transactions on Emerging Topics in Computing.

Efficient surface-wave-based network-on-chip architecture for spiking-neural-network

Terrence Mak, Alex Yakovlev, Ammar J. M. Karkar, 2017, 2017 Annual Conference on New Trends in Information & Communications Technology Applications (NTICT).

Hybrid wire-surface wave interconnects for next-generation networks-on-chip

Terrence S. T. Mak, Alexandre Yakovlev, Fei Xia, 2013, IET Comput. Digit. Tech..

Wave-pipelined intra-chip signaling for on-FPGA communications

Wayne Luk, Terrence S. T. Mak, Peter Y. K. Cheung, 2010, Integr..

A Resilient 2-D Waveguide Communication Fabric for Hybrid Wired-Wireless NoC Design

Terrence Mak, Alexandre Yakovlev, Quoc-Tuan Vien, 2017, IEEE Transactions on Parallel and Distributed Systems.

An Efficient Channel Model for Evaluating Wireless NoC Architectures

Terrence S. T. Mak, Gary Hill, Scott J. Turner, 2016, 2016 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW).

An Analytical Channel Model for Emerging Wireless Networks-on-Chip

Terrence S. T. Mak, Quoc-Tuan Vien, Michael Opoku Agyeman, 2016, 2016 IEEE Intl Conference on Computational Science and Engineering (CSE) and IEEE Intl Conference on Embedded and Ubiquitous Computing (EUC) and 15th Intl Symposium on Distributed Computing and Applications for Business Engineering (DCABES).

A Survey of Wireless Sensor Network Based Air Pollution Monitoring Systems

Kwong-Sak Leung, Yee Leung, Terrence S. T. Mak, 2015, Sensors.

Real-Time Simulation of Passage-of-Time Encoding in Cerebellum Using a Scalable FPGA-Based System

Tadashi Yamazaki, Terrence S. T. Mak, Patrick Degenaar, 2016, IEEE Transactions on Biomedical Circuits and Systems.

Thermal and Performance Efficient On-Chip Surface-Wave Communication for Many-Core Systems in Dark Silicon Era

K. Tong, T. Mak, Ammar Karkar, 2022, ACM J. Emerg. Technol. Comput. Syst..

A Current-Mode Analog Circuit for Reinforcement Learning Problems

Chi-Sang Poon, Terrence S. T. Mak, Kai-Pui Lam, 2007, 2007 IEEE International Symposium on Circuits and Systems.

A Novel Partitioning Algorithm for Optimizing Neuron-to-Neuron Pathways through NoC in BMI

Terrence S. T. Mak, Jim Ng, T. Mak, 2014, NoCArc '14.

Minterm based synthesis and optimization of asynchronous dual-rail encoded functional modules

Terrence Mak, Yu Zhou, Qing Xu, 2017, 2017 International Conference on Circuits, Devices and Systems (ICCDS).

Low-power 3D integration using inductive coupling links for neurotechnology applications

Chi-Sang Poon, Shidhartha Das, Terrence S. T. Mak, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Real-time neuronal networks reconstruction using hierarchical systolic arrays

Bo Yu, Chi-Sang Poon, Terrence S. T. Mak, 2011, 2011 Annual International Conference of the IEEE Engineering in Medicine and Biology Society.

A Survey of Emerging Interconnects for On-Chip Efficient Multicast and Broadcast in Many-Cores

Terrence Mak, Kin-Fai Tong, Alex Yakovlev, 2016, IEEE Circuits and Systems Magazine.

Equivalence-set genes partitioning using an evolutionary-DP approach

T. Mak, K. Lam, 2005, IEEE Transactions on NanoBioscience.

Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network

Wayne Luk, Terrence S. T. Mak, Peter Y. K. Cheung, 2011, IEEE Transactions on Industrial Electronics.

Surface wave communication system for on-chip and off-chip interconnects

Terrence S. T. Mak, Alexandre Yakovlev, Ra'ed Al-Dujaily, 2012, NoCArc '12.

Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting

Terrence S. T. Mak, Alexandre Yakovlev, Kin-Fai Tong, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC

Chi-Sang Poon, Terrence S. T. Mak, Kai-Pui Lam, 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.

Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network

Chi-Sang Poon, Terrence S. T. Mak, Kai-Pui Lam, 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.

A CMOS Current-Mode Dynamic Programming Circuit

Chi-Sang Poon, Terrence S. T. Mak, Kai-Pui Lam, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing

Wayne Luk, Terrence S. T. Mak, Peter Y. K. Cheung, 2007, First International Symposium on Networks-on-Chip (NOCS'07).

Modular sensor system (MSS) for urban air pollution monitoring

Kwong-Sak Leung, Terrence Mak, Wei-Ying Yi, 2016, 2016 IEEE SENSORS.

Real-Time FPGA-Based Multichannel Spike Sorting Using Hebbian Eigenfilters

Xiangyu Li, Alexandre Yakovlev, Fei Xia, 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

A Genetic Algorithm with New Local Operators for Multiple Traveling Salesman Problems

Kwong-Sak Leung, Yee Leung, Terrence S. T. Mak, 2018, Int. J. Comput. Intell. Syst..

Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network Perspective

Yingtao Jiang, Terrence Mak, Xiaohang Wang, 2021, IEEE Access.

Molecular Type Spread Molecular Shift Keying for Multiple-Access Diffusive Molecular Communications

Lie-Liang Yang, Terrence Mak, Weidong Gao, 2021, IEEE Transactions on Molecular, Biological and Multi-Scale Communications.

Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach

Terrence S. T. Mak, Alexandre Yakovlev, Nizar Dahir, 2021, Integr..

An Improved Wireless Communication Fabric for Performance Aware Network-on-Chip Architectures

Terrence Mak, Michael Opoku Agyeman, Kenneth Tong, 2016 .

Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip

Xiaohang Wang, Terrence S. T. Mak, Liang Wang, 2014, VLSI-SoC.

Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems

Tao Zhang, Wayne Luk, Terrence S. T. Mak, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An integrated web-based air pollution decision support system – a prototype

Kwong-Sak Leung, Yee Leung, Terrence S. T. Mak, 2018, Int. J. Geogr. Inf. Sci..

Dynamic programming-based runtime thermal management (DPRTM)

Terrence S. T. Mak, Alexandre Yakovlev, Nizar Dahir, 2013, ACM Trans. Design Autom. Electr. Syst..

Run-time deadlock detection in networks-on-chip using coupled transitive closure networks

Terrence S. T. Mak, Alexandre Yakovlev, Fei Xia, 2011, 2011 Design, Automation & Test in Europe.

On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach

Terrence S. T. Mak, Kai-Pui Lam, K. Lam, 2002, FPL.

On-Chip Systolic Networks for Real-Time Tracking of Pairwise Correlations Between Neurons in a Large-Scale Network

Bo Yu, Chi-Sang Poon, Terrence S. T. Mak, 2013, IEEE Transactions on Biomedical Engineering.

Highly adaptive and deadlock-free routing for three-dimensional networks-on-chip

Terrence S. T. Mak, Alexandre Yakovlev, Nizar Dahir, 2013, IET Comput. Digit. Tech..

Field programmable gate arrays and analog implementation of BRIN for optimization problems

Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Eliminating Synchronization Latency Using Sequenced Latching

Terrence S. T. Mak, Alexandre Yakovlev, Ghaith Tarawneh, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Run-Time Concurrency Tuning for Peak Power Modulation in Energy Harvesting Systems

Terrence S. T. Mak, Alexandre Yakovlev, Yu Zhou, 2011, 2011 Eleventh International Conference on Application of Concurrency to System Design.

Circuit design and analysis for on-FPGA communication systems

Terrence Sui-Tung Mak, T. Mak, 2009 .

Interconnection lengths and delays estimation for communication links in FPGAs

Wayne Luk, Terrence S. T. Mak, Peter Y. K. Cheung, 2008, SLIP '08.

Global interconnections in FPGAs: modeling and performance analysis

Wayne Luk, Terrence S. T. Mak, Alexandre Yakovlev, 2008, SLIP '08.

The Future Looks Gloomy for FPGA Interconnects

Terrence Mak, T. Mak, 2009 .

Design and Optimization of Inductive-Coupling Links for 3-D-ICs

Shidhartha Das, Terrence Mak, Benjamin J. Fletcher, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design and Implementation of Dynamic Thermal-Adaptive Routing Strategy for Networks-on-Chip

Terrence S. T. Mak, Alexandre Yakovlev, Nizar Dahir, 2014, 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing.