Mário P. Véstias

发表

Processing Systems for Deep Learning Inference on Edge Devices

Mário P. Véstias, 2020, Convergence of Artificial Intelligence and the Internet of Things.

Area/Performance Improvement of NoC Architectures

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2006, ARC.

A reconfigurable computing architecture using magnetic tunneling junction memories

Mário P. Véstias, Jorge R. Fernandes, Horácio C. Neto, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

High-Performance Reconfigurable Computing Granularity

Mário P. Véstias, 2015 .

Efficient implementation of a single-precision floating-point arithmetic unit on FPGA

Mário P. Véstias, Horácio C. Neto, Ana Rita Silva, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Non-volatile memory circuits for FIMS and TAS writing techniques on magnetic tunnelling junctions

Mário P. Véstias, Jorge R. Fernandes, Horácio C. Neto, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

Design and test of a MIMO Receiver based on the Alamouti scheme in FPGA

Mário P. Véstias, 2012, 2012 IEEE Second International Conference on Consumer Electronics - Berlin (ICCE-Berlin).

Run-Time Reconfigurable Array Using Magnetic RAM

Mário P. Véstias, Luís Bica Oliveira, Jorge R. Fernandes, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

A Survey of Convolutional Neural Networks on Edge with Reconfigurable Computing

Mário P. Véstias, M. Véstias, 2019, Algorithms.

Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs

Mário P. Véstias, Horácio C. Neto, Rui Policarpo Duarte, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

Analysis of matrix multiplication on high density Virtex-7 FPGA

Mário P. Véstias, Horácio C. Neto, Ana Rita Silva, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

Decimal multiplier on FPGA using embedded binary multipliers

Mário P. Véstias, Horácio C. Neto, 2008, 2008 International Conference on Field Programmable Logic and Applications.

Designing Hardware/Software Systems for Embedded High-Performance Computing pdf

Mário P. Véstias, Horácio C. Neto, Rui Policarpo Duarte, 2015, ArXiv.

Improving the area of fast parallel decimal multipliers

Mário P. Véstias, Horácio C. Neto, 2018, Microprocess. Microsystems.

K-means clustering on CGRA

Mário P. Véstias, José T. de Sousa, Horácio C. Neto, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

Tradeoffs in the design of sliding block Viterbi decoders for MB-OFDM UWB systems

Mário P. Véstias, Helena Sarmento, 2012, 2012 IEEE Second International Conference on Consumer Electronics - Berlin (ICCE-Berlin).

Implementing CNNs Using a Linear Array of Full Mesh CGRAs

Mário P. Véstias, José T. de Sousa, João D. Lopes, 2020, ARC.

Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2007, 2007 International Conference on Field Programmable Logic and Applications.

DALI: a methodology for the co-design of dataflow applications on hardware/software architectures [video encoder DSP example]

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

Enhancing stochastic computations via process variation

Mário P. Véstias, Horácio C. Neto, Rui Policarpo Duarte, 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

Multiplier-based double precision floating point divider according to the IEEE-754 standard

Mário P. Véstias, Horácio C. Neto, Rui Policarpo Duarte, 2008, ARC.

Co-synthesis of a configurable SoC platform based on a network on chip architecture

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Revisiting the Newton-Raphson Iterative Method for Decimal Division

Mário P. Véstias, Horácio C. Neto, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

Sliding block Viterbi decoders in FPGA

Mário P. Véstias, Horácio C. Neto, Helena Sarmento, 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

A Many-Core Overlay for High-Performance Embedded Computing on FPGAs pdf

Mário P. Véstias, Horácio C. Neto, 2014, ArXiv.

Parallel dot-products for deep learning on FPGA

Mário P. Véstias, José T. de Sousa, Horácio C. Neto, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder on FPGA

Mário P. Véstias, Tiago Rodrigues, 2015, 2015 Euromicro Conference on Digital System Design.

Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs

Mário P. Véstias, Tiago Peres, Ana Gonçalves, 2019, ARC.

Design of an IEEE 802.15.3c baseband processor in FPGA

Mário P. Véstias, Helena Sarmento, 2012, 2012 IEEE Second International Conference on Consumer Electronics - Berlin (ICCE-Berlin).

XtokaxtikoX: A stochastic computing-based autonomous cyber-physical system

Mário P. Véstias, Horácio C. Neto, Rui Policarpo Duarte, 2016, 2016 IEEE International Conference on Rebooting Computing (ICRC).

Trends of CPU, GPU and FPGA for high-performance computing

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's Algorithm

Mário P. Véstias, Horácio C. Neto, 2012, 2012 15th Euromicro Conference on Digital System Design.

A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs

Mário P. Véstias, Horácio C. Neto, Rui P. Duarte, 2020, IEEE Access.

System-level co-synthesis of dataflow dominated applications on reconfigurable hardware/software architectures

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2002, Proceedings 13th IEEE International Workshop on Rapid System Prototyping.

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Mário P. Véstias, Horácio C. Neto, Ana Rita Silva, 2015 .

FPGA-based architecture for hyperspectral unmixing

Mário P. Véstias, José M. P. Nascimento, Gabriel Martín, 2015, 2015 IEEE International Geoscience and Remote Sensing Symposium (IGARSS).

A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory

Mário P. Véstias, Jorge R. Fernandes, Horácio C. Neto, 2012, 2012 International Conference on Reconfigurable Computing and FPGAs.

Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores

Mário P. Véstias, José T. de Sousa, Rui Policarpo Duarte, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs

Mário P. Véstias, Horácio C. Neto, Helena Sarmento, 2012, 2012 15th Euromicro Conference on Digital System Design.

Faster Convolutional Neural Networks in Low Density FPGAs Using Block Pruning

Mário P. Véstias, Tiago Peres, Ana Gonçalves, 2019, ARC.

A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Decimal addition on FPGA based on a mixed BCD/excess-6 representation

Mário P. Véstias, Horácio C. Neto, 2017, Microprocess. Microsystems.

Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture

Mário P. Véstias, Horácio C. Neto, Wilson Jose, 2015, 2015 Euromicro Conference on Digital System Design.

Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs

Mário P. Véstias, José T. de Sousa, Horácio C. Neto, 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).

Very low resource table-based FPGA evaluation of elementary functions

Mário P. Véstias, Horácio C. Neto, 2013, 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig).

Area and performance optimization of a generic network-on-chip architecture

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2006, SBCCI '06.

Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA

Mário P. Véstias, José T. de Sousa, Horácio C. Neto, 2019, 2019 29th International Conference on Field Programmable Logic and Applications (FPL).

Coarse-Grained Reconfigurable Computing with the Versat Architecture

Mário P. Véstias, Horácio C. Neto, João D. Lopes, 2021 .

A Full Featured Configurable Accelerator for Object Detection With YOLO

Mário P. Véstias, Horácio C. Neto, João D. Lopes, 2021, IEEE Access.

Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor

Mário P. Véstias, Horácio C. Neto, 2021, Algorithms.

Configurable Hardware Core for IoT Object Detection

Mário P. Véstias, José T. de Sousa, Horácio C. Neto, 2021, Future Internet.

IOb-Cache: A High-Performance Configurable Open-Source Cache

Mário P. Véstias, José T. de Sousa, João D. Lopes, 2021, Algorithms.